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公开(公告)号:US20190237401A1
公开(公告)日:2019-08-01
申请号:US16377626
申请日:2019-04-08
发明人: Kazuhide Abe
IPC分类号: H01L23/522 , H01L23/532 , H01L21/768 , H01L21/3213 , H01L21/321 , H01L21/311 , H01L21/288
CPC分类号: H01L23/5226 , H01L21/2885 , H01L21/31116 , H01L21/3212 , H01L21/32135 , H01L21/32136 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76834 , H01L21/76844 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.
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2.
公开(公告)号:US20190157211A1
公开(公告)日:2019-05-23
申请号:US16257171
申请日:2019-01-25
发明人: Hyunjae SONG , Seunggeol Nam , Yeonchoo Cho , Seongjun Park , Hyeonjin Shin , Jaeho Lee
IPC分类号: H01L23/532 , H01L21/768 , H01L23/522
CPC分类号: H01L23/53209 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76852 , H01L23/5226
摘要: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
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公开(公告)号:US20190157133A1
公开(公告)日:2019-05-23
申请号:US16238172
申请日:2019-01-02
发明人: Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC分类号: H01L21/768 , H01L23/535 , H01L27/108 , H01L23/532
CPC分类号: H01L21/7682 , H01L21/76805 , H01L21/76849 , H01L21/76895 , H01L23/5329 , H01L23/535 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876
摘要: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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公开(公告)号:US20180350664A1
公开(公告)日:2018-12-06
申请号:US15801179
申请日:2017-11-01
发明人: Nai-Chia Chen , Chun-Li Chou , Yen-Chiu Kuo , Chun-Hung Chao , Yu-Li Cheng
IPC分类号: H01L21/768 , H01L21/02 , H01L23/522 , H01L23/528 , B08B3/02 , B08B3/08
CPC分类号: H01L21/76814 , B08B3/024 , B08B3/08 , H01L21/02063 , H01L21/02101 , H01L21/31116 , H01L21/31144 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/5283
摘要: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
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公开(公告)号:US20180323226A1
公开(公告)日:2018-11-08
申请号:US15922514
申请日:2018-03-15
申请人: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
发明人: DEKUI QI , Fucheng Chen
IPC分类号: H01L27/146 , H01L21/28 , H01L21/768 , H01L21/3213
CPC分类号: H01L27/1464 , H01L21/28123 , H01L21/3213 , H01L21/76834 , H01L21/76849 , H01L27/14603 , H01L27/14645
摘要: A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and having a bottom at a depth the same as an upper surface of the metal wire, a first insulation layer including a first color filter material on sidewalls of the first opening, a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening, and a second insulation layer including a second color filter material on sidewalls of the second opening. The first opening is for leading out the metal wire to a pad. The second opening is disposed along scribe lines. The semiconductor device simplifies the process of drawing out and isolating the pads and satisfies technical requirements of a back seal ring.
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公开(公告)号:US20180277482A1
公开(公告)日:2018-09-27
申请号:US15811129
申请日:2017-11-13
发明人: Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert
IPC分类号: H01L23/528 , H01L23/532 , H01L23/522 , H01L21/768 , H01L21/02
CPC分类号: H01L23/5283 , H01L21/02167 , H01L21/76816 , H01L21/76828 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L23/5222 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295
摘要: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
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公开(公告)号:US10062606B2
公开(公告)日:2018-08-28
申请号:US15837132
申请日:2017-12-11
发明人: Yongkong Siew , Seongho Park
IPC分类号: H01L21/768 , H01L23/522 , H01L23/532
CPC分类号: H01L21/76844 , H01L21/76847 , H01L21/76849 , H01L21/76879 , H01L23/5226 , H01L23/53238 , H01L23/53266
摘要: Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, and forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure. The methods include etching the middle interlayer insulating layer to form a via hole and an interconnection trench vertically aligned with the via hole, and forming a via barrier layer on inner walls of the via hole and an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on an upper surface of the conductive base structure The methods include forming a via plug on the via barrier layer to fill the via hole, forming a seed layer on the interconnection trench and the via plug, forming an interconnection electrode on the seed layer, and forming an interconnection capping layer on the interconnection electrode.
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8.
公开(公告)号:US20180240705A1
公开(公告)日:2018-08-23
申请号:US15472295
申请日:2017-03-29
发明人: Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Fu-Che Lee , Ming-Feng Kuo
IPC分类号: H01L21/768 , H01L21/762 , H01L21/311 , H01L21/02 , H01L23/535 , H01L29/06
CPC分类号: H01L21/76895 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76224 , H01L21/76805 , H01L21/76814 , H01L21/76849 , H01L23/528 , H01L23/535 , H01L27/10888 , H01L29/0649
摘要: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
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公开(公告)号:US10014212B2
公开(公告)日:2018-07-03
申请号:US15622510
申请日:2017-06-14
申请人: ASM IP HOLDING B.V.
发明人: Shang Chen , Toshiharu Watarai , Takahiro Onuma , Dai Ishikawa , Kunitoshi Namba
IPC分类号: H01L21/768 , H01L21/285 , H01L23/532
CPC分类号: H01L21/7685 , H01L21/02068 , H01L21/28562 , H01L21/28568 , H01L21/3105 , H01L21/76823 , H01L21/76826 , H01L21/76849 , H01L21/76868 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53266
摘要: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
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公开(公告)号:US20180174903A1
公开(公告)日:2018-06-21
申请号:US15897526
申请日:2018-02-15
发明人: Conal E. Murray , Chih-Chao Yang
IPC分类号: H01L21/768 , H01L23/532 , C23F4/00 , C23F1/44 , H01L23/528 , H01L23/522
CPC分类号: H01L21/76879 , C23F1/44 , C23F4/00 , H01L21/76802 , H01L21/76804 , H01L21/76805 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.
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