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公开(公告)号：US08188761B2
公开(公告)日：2012-05-29
申请号：US13026472
申请日：2011-02-14
IPC分类号： H03K19/003
CPC分类号： H03K3/0375
摘要： A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.
摘要翻译： 公开了一种用于数字IC中的软错误检测的系统和方法。 该系统包括耦合到锁存器的观察电路，该电路能够在锁存器的状态改变时作出响应。 该系统还包括提供给锁存器和观察电路的同步时钟。 对于锁存器，时钟定义了时间窗口，在该窗口期间锁存器被阻止接收数据，并且以同步方式，时钟使能在观察电路中的响应。 时钟同步，使得当锁存器被阻止接收数据时，电路只能在窗口内使其响应。 系统还可以具有分别耦合到锁存器的附加电路，其中每个附加电路及其相应的锁存器接收多个电路的同步时钟响应可以以对应于逻辑或的配置耦合。
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公开(公告)号：US08127078B2
公开(公告)日：2012-02-28
申请号：US12572416
申请日：2009-10-02
IPC分类号： G06F12/00
CPC分类号： G06F12/0886
摘要： A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache line, and a second cache array coupled to an alignment unit is configured to output a second cache entry associated with the alignment cache line. The alignment unit coupled to the address decoder selects either the target cache line or a neighbor cache line proximate the target cache line as an alignment cache line output. Selection of either the target cache line or a neighbor cache line is based on an alignment bit in the memory address. A tag array cache is split into even and odd cache lines tags, and provides one or two tags for every cache access.
摘要翻译： 一种高速缓冲存储器件及其操作方法。 高速缓冲存储器设备的一个实施例包括解码存储器地址并选择目标高速缓存行的地址译码器。 第一高速缓存阵列被配置为输出与目标高速缓存行相关联的第一高速缓存条目，并且耦合到对准单元的第二高速缓存阵列被配置为输出与对准高速缓存行相关联的第二高速缓存条目。 耦合到地址解码器的对准单元选择目标高速缓存线或邻近目标高速缓存行的相邻高速缓存行作为对准高速缓存行输出。 目标高速缓存行或相邻高速缓存行的选择基于存储器地址中的对齐位。 标签数组高速缓存分为偶数和奇数缓存行标签，并为每个高速缓存访问提供一个或两个标签。
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公开(公告)号：US08030649B2
公开(公告)日：2011-10-04
申请号：US11460751
申请日：2006-07-28
申请人： Michael K. Gschwind
发明人： Michael K. Gschwind
CPC分类号： G01R31/318569
摘要： Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to outputs of the scan chains. The verification unit is configured to determine the validity of the outputs of the scan chains and to indicate a malfunction of the integrated circuit if the outputs are determined not to be valid.
摘要翻译： 用于在集成电路中测试多核处理器的各种技术。 每个核心包括配置成形成至少两个扫描链的多个寄存器。 在一个实施例中，位于集成电路中的验证单元电耦合到扫描链的输出端。 验证单元被配置为确定扫描链的输出的有效性并且如果确定输出无效则指示集成电路的故障。
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54.发明授权Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine 失效用于编译单指令多数据（SIMD）执行引擎的标量代码的方法公开(公告)号：US08010953B2
公开(公告)日：2011-08-30
申请号：US11278639
申请日：2006-04-04
申请人： Michael K. Gschwind
发明人： Michael K. Gschwind
CPC分类号： G06F9/3013 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/3885 , G06F9/3887
摘要： Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.
摘要翻译： 提供使用SIMD数据并行执行单元执行标量运算。 利用说明性实施例的机制，识别可以使用SIMD数据并行执行单元中的向量操作来执行应用代码中的标量运算。 标量运算例如通过静态或动态编译器被转换成一个或多个向量加载指令和一个或多个向量计算指令。 此外，可以生成控制字以使用向量加载指令调整加载了这些标量值的向量寄存器内的标量运算的标量值的对齐。 用于调整向量寄存器内的标量值的对准量可以是静态或动态地确定的。
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公开(公告)号：US20110047334A1
公开(公告)日：2011-02-24
申请号：US12544704
申请日：2009-08-20
CPC分类号： G06F12/0842 , G06F11/1405
摘要： Mechanisms for generating checkpoints in a speculative versioning cache of a data processing system are provided. The mechanisms execute code within the data processing system, wherein the code accesses cache lines in the speculative versioning cache. The mechanisms further determine whether a first condition occurs indicating a need to generate a checkpoint in the speculative versioning cache. The checkpoint is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint in the speculative versioning cache in response to a determination that the first condition has occurred.
摘要翻译： 提供了用于在数据处理系统的推测版本缓存中生成检查点的机制。 这些机制在数据处理系统内执行代码，其中代码访问推测版本控制缓存中的高速缓存行。 这些机制进一步确定是否出现指示在推测版本控制高速缓存中生成检查点的需要的第一条件。 检查点是推测性高速缓存行，其响应于需要向对应于推测性高速缓存行的高速缓存行的回滚而返回的第二条件而变得不推测。 这些机制还响应于确定第一个条件已经发生，在推测版本控制缓存中生成检查点。
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56.发明申请Complex Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture 失效在高性能计算架构中使用数据预处理的复杂矩阵乘法运算公开(公告)号：US20110040822A1
公开(公告)日：2011-02-17
申请号：US12542324
申请日：2009-08-17
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109
摘要： Mechanisms for performing a complex matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the complex matrix multiplication operation to a first target vector register. The first vector operand comprises a real and imaginary part of a first complex vector value. A complex load and splat operation is performed to load a second complex vector value of a second vector operand and replicate the second complex vector value within a second target vector register. The second complex vector value has a real and imaginary part. A cross multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the complex matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored in a result vector register.
摘要翻译： 提供了执行复矩阵乘法运算的机制。 执行矢量加载操作以将复矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。 第一矢量操作数包括第一复矢量值的实部和虚部。 执行复杂的加载和拼接操作以加载第二向量操作数的第二复数向量值，并在第二目标向量寄存器内复制第二复数向量值。 第二个复矢量值具有实部和虚部。 对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行交叉乘法运算，以生成复矩阵乘法运算的部分乘积。 部分产品与其他部分产品一起累积，并将结果积累的部分产品存储在结果向量寄存器中。
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57.发明授权Method and structure for low latency load-tagged pointer instruction for computer microarchitechture 有权用于计算机微型计算机的低延迟负载标记指针指令的方法和结构公开(公告)号：US07849293B2
公开(公告)日：2010-12-07
申请号：US12023791
申请日：2008-01-31
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/30072 , G06F9/30192 , G06F9/3842
摘要： A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal instruction execution latency. A second higher latency, non-speculative implementation that always produces correct results is invoked by the first when the first guesses incorrectly. The methodologies and structures disclosed herein are intended to be combined with predictive techniques for instruction processing to ultimately improve processing throughput.
摘要翻译： 介绍了基于RISC的微体系结构的负载标记指针指令的方法和实现。 第一个较低的等待时间，推测性实现通过估计特定指令的结果并确认估计的完整性比正常指令执行等待时间慢一点来减少微处理器系统的总吞吐量等待时间。 当第一次猜测不正确时，第一个更高延迟，非推测性实现始终产生正确的结果。 本文公开的方法和结构旨在与指令处理的预测技术组合以最终提高处理吞吐量。
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58.发明授权公开(公告)号：US07620756B2
公开(公告)日：2009-11-17
申请号：US11507306
申请日：2006-08-21
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译： 一种用于从窄总线（m位，其中m
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公开(公告)号：US20090198966A1
公开(公告)日：2009-08-06
申请号：US12023720
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30
CPC分类号： G06F9/3013 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30145
摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.
摘要翻译： 可以使用标量和SIMD指令来寻址单个寄存器文件。 也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式 的指令，这里称为矢量 - 标量延伸（VSX）指令。 可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。 这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。
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公开(公告)号：US20090119494A1
公开(公告)日：2009-05-07
申请号：US11933774
申请日：2007-11-01
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3005 , G06F9/30072 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/30181 , G06F9/3804 , G06F9/3842 , G06F9/3846 , G06F9/3848 , G06F9/3861
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior instruction execution characteristics; logic for obtaining predictor information for the fetched instruction from the predictor; and decode logic for generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction, wherein the decode operation stream is selected based on the predictor information.
摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于预测解码的装置，该装置包括用于取指令的寄存器逻辑; 包含预测器信息的预测器逻辑，包括先前的指令执行特性; 用于从预测器获取所获取的指令的预测信息的逻辑; 以及解码逻辑，用于产生对应于获取的指令的多个解码操作流中的所选择的一个解码操作流，其中基于预测器信息来选择解码操作流。
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