公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20220066876A1

公开(公告)日：2022-03-03

申请号：US17004136

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C11/408

Abstract: A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.

公开(公告)号：US20210390014A1

公开(公告)日：2021-12-16

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/0882 ,  G06F11/07 ,  G06F12/02

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.