公开(公告)号：US11513889B2

公开(公告)日：2022-11-29

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10685731B2

公开(公告)日：2020-06-16

申请号：US16410764

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Scott Anthony Stoller ,  Preston Allen Thomson ,  Devin Batutis ,  Harish Reddy Singidi ,  Kulachet Tanpairoj

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G06F11/07 ,  G11C29/50 ,  G06F11/10

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

公开(公告)号：US20190333585A1

公开(公告)日：2019-10-31

申请号：US16504039

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C16/10 ,  G11C16/22 ,  G11C29/02 ,  G11C16/34 ,  G11C11/56 ,  G11C16/28 ,  G11C16/20 ,  G11C16/04

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US11482298B2

公开(公告)日：2022-10-25

申请号：US16887592

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Jason Lee Nevill ,  Preston Allen Thomson ,  Chi Ming Chu ,  Sheng-Huang Lee

IPC: G11C29/50 ,  G11C5/14 ,  G11C7/10 ,  G11C8/08

Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

公开(公告)号：US20210287748A1

公开(公告)日：2021-09-16

申请号：US17331395

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US10950310B2

公开(公告)日：2021-03-16

申请号：US16727472

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10824527B2

公开(公告)日：2020-11-03

申请号：US16504067

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G11C16/34 ,  G06F11/20 ,  G11C29/00 ,  G06F11/10 ,  G11C16/04

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US11735269B2

公开(公告)日：2023-08-22

申请号：US17589172

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C8/00 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3445 ,  G11C11/5671 ,  G11C16/3409 ,  H10B41/27 ,  H10B43/27

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US11238939B2

公开(公告)日：2022-02-01

申请号：US17158555

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US11106530B2

公开(公告)日：2021-08-31

申请号：US16723836

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.