公开(公告)号：US5235536A

公开(公告)日：1993-08-10

申请号：US762348

申请日：1991-09-19

申请人： Noritsugu Matsubishi ,  Yoshio Tokuno ,  Hiroshi Masaki ,  Masato Yamazaki

发明人： Noritsugu Matsubishi ,  Yoshio Tokuno ,  Hiroshi Masaki ,  Masato Yamazaki

IPC分类号： G06F7/505 ,  G06F7/53 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F7/57 ,  G06F17/16 ,  G06F7/544 ,  G06F7/5443 ,  G06F2207/5442

摘要： A processing unit for executing parallel cumulative absolute difference operations in a first mode, and an inner product operation in a second mode, includes an input bus group for receiving first input data, second input data, and third input data. A plurality of processor elements are coupled to the input bus group, each processor element being coupled to compute a cumulative absolute difference between the first input data and the second input data in the first mode, and to compute and accumulate one term of Booth's algorithm for multiplying the first input data by the third input data in the second mode. An output bus group is coupled to the processor elements, for receiving the terms of Booth's algorithm. An accumulator circuit is coupled to the output bus group, for shifting and adding terms of Booth's algorithm output by the processor elements.