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公开(公告)号：US20080229989A1
公开(公告)日：2008-09-25
申请号：US11905570
申请日：2007-10-02
申请人： Atsushi Shiraishi
发明人： Atsushi Shiraishi
IPC分类号： D05B65/00
摘要： A thread cutting device includes a thread catching member having a catching portion, wherein the thread catching member moves back and forth across a path of a lower thread reeled out from a bobbin so as to catch the lower thread by the catching portion and cuts the lower thread by cooperating with a fixed knife, a first power transmitting portion which transmits a power to the thread catching member, a first cam member provided on a lower shaft rotated by a sewing machine motor and transmits a first moving force to the thread catching member through the first power transmitting portion, a second power transmitting portion which transmits a second moving force from a stepping motor to the thread catching member through the first power transmitting portion.
摘要翻译： 螺纹切割装置包括具有捕获部分的螺纹捕获构件，其中，所述抓线构件沿着从筒管卷出的下线的路径来回移动，以便通过捕获部分抓住下螺纹并切割下部 螺纹通过与固定刀配合，将第一动力传递部分向牵引构件传递动力;第一凸轮构件，设置在由缝纫机马达旋转的下轴上，并将第一移动力传递到抓线构件，该第一移动力通过 第一动力传递部分，第二动力传递部分，其通过第一动力传递部分将来自步进马达的第二移动力传递到抓线部件。
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公开(公告)号：US07343445B2
公开(公告)日：2008-03-11
申请号：US11541543
申请日：2006-10-03
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
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公开(公告)号：US07305589B2
公开(公告)日：2007-12-04
申请号：US10484043
申请日：2002-05-08
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较 ROM4a的数据FD1 <2> 。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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公开(公告)号：US20070150649A1
公开(公告)日：2007-06-28
申请号：US11709778
申请日：2007-02-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C16/102
摘要： A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.
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公开(公告)号：US07216597B2
公开(公告)日：2007-05-15
申请号：US11442184
申请日：2006-05-26
申请人： Atsushi Shiraishi
发明人： Atsushi Shiraishi
CPC分类号： D05B87/02
摘要： A threading device for a sewing machine includes a needle bar provided with a guide member having a stopper portion, a threading shaft having a threading member, operation means having a guide groove formed in a spiral shape with respect to a rotating axis of the threading shaft, and a pin, which is fixed to the threading shaft, having both ends protruded outward in a radial direction with respect to the threading shaft. One end of the pin penetrates the guide groove while the other end of the pin engages with the stopper portion. The threading device further includes erroneous rotation preventing means which prevents the threading shaft from rotating in when the threading shaft moves downward, and permits the threading shaft to rotate when the second end of the pin engages with the stopper portion.
摘要翻译： 缝纫机用的穿线装置包括具有带止动部的引导部件的针杆，具有穿线部件的穿线轴，具有相对于穿线轴的旋转轴成螺旋状的导向槽的操作机构 以及固定在穿线轴上的销，其两端相对于穿线轴在径向向外突出。 销的一端穿过引导槽，而销的另一端与止动部分接合。 穿线装置还包括错误旋转防止装置，当穿线轴向下移动时防止穿线轴旋转，并且当销的第二端与止动部分接合时允许穿线轴旋转。
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公开(公告)号：US07197595B2
公开(公告)日：2007-03-27
申请号：US10721362
申请日：2003-11-26
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C16/102
摘要： A nonvolatile memory has plural memory blocks, each having a plurality of sub memory blocks, and is capable of programming to a first sub memory block within a first memory block and a second sub memory block within a second memory block in parallel. The first sub memory block has a management area for storing a management information including linking information between the first sub memory block corresponding sub memory blocks of other memory blocks. A control circuit controls reading the linking information from the first sub memory block in accordance with address information, and programming to the first sub memory block in accordance with the address information and corresponding sub memory blocks by the linking information.
摘要翻译： 非易失性存储器具有多个存储块，每个存储块具有多个子存储块，并且能够并行地编程到第一存储块内的第一子存储块和第二存储块内的第二子存储块。 第一子存储块具有用于存储管理信息的管理区域，该管理信息包括第一子存储块对应的其他存储块的子存储块之间的链接信息。 控制电路根据地址信息控制从第一子存储块读取链接信息，并根据地址信息和对应的子存储块通过链接信息对第一子存储块进行编程。
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公开(公告)号：US07133961B2
公开(公告)日：2006-11-07
申请号：US10195400
申请日：2002-07-16
IPC分类号： G06F12/00
CPC分类号： G06K19/07 , G11C16/102
摘要： A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
摘要翻译： 存储卡设置有传送控制电路，写入控制电路和判断电路。 传送控制电路在数据传送期间输出传送标志信号。 写入控制电路在数据写入操作期间输出内部忙信号。 当输入传送平面信号期间主机的卡选择信号被否定时，判断电路输出传送中断信号，并且当在内部忙信号的输入期间卡选择信号被否定时，输出暂停信号。 CPU在接收到传送中断信号时使传送数据中断传输处理，并且在接收到暂停信号时完成正在执行的处理并处于等待状态。 因此，即使当不符合标准的定时信号被传送时，主机也可以从内部处理条件中选择最佳处理操作，从而执行所选择的操作。
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公开(公告)号：US20060228910A1
公开(公告)日：2006-10-12
申请号：US11449816
申请日：2006-06-09
IPC分类号： H05K1/00
CPC分类号： G06K19/07732 , G06K19/07 , G06K19/0719 , G06K19/072 , G06K19/07733 , G06K19/07743 , H01L2224/05553 , H01L2224/48137 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/14
摘要： A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot, wherein the amounts of protrusion of slot terminals in a card slot are alternately changed in association with a zigzag section, and the slot terminals are disposed in a row in parallel as a whole.
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公开(公告)号：US07104714B2
公开(公告)日：2006-09-12
申请号：US11107570
申请日：2005-04-14
CPC分类号： B41J13/10 , B41J11/0045
摘要： A printer includes a transporting block, a printing block, a positioning block, and an intermediate picking-up device. The positioning block is disposed between the transporting block and the printing block, and positions printing sheets transported by the transporting block at a predetermined location one at a time, so that they are positioned one at a time at a printing location of the printing block where printing is performed on the printing sheets. The intermediate picking-up means picks up the printing sheets positioned at the predetermined location in the positioning block one at a time in order to transport the printing sheets to the printing block.
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公开(公告)号：US20060157573A1
公开(公告)日：2006-07-20
申请号：US11378277
申请日：2006-03-20
IPC分类号： G06K19/06
CPC分类号： G06K19/07732 , G06K19/07743 , G11C5/066 , H01L25/18 , H01L2223/54406 , H01L2223/54486 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2225/06562 , H01L2924/01021 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/3011 , H05K1/117 , H01L2924/00 , H01L2924/00012
摘要： An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
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