公开(公告)号：US20240312950A1

公开(公告)日：2024-09-19

申请号：US18439249

申请日：2024-02-12

Applicant: Renesas Electronics Corporation

Inventor： Takaya HOSHI ,  Fumiaki AGA

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/49 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49051 ,  H01L2224/49052 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2924/386

Abstract: A plurality of wires of a semiconductor device includes: a first wire connected to each of an end portion electrode and a first terminal of a plurality of terminals; and a second wire connected to each of a non-end portion electrode and a second terminal of the plurality of terminals. A loop height of the first wire is greater than a loop height of the second wire.

公开(公告)号：US20240164118A1

公开(公告)日：2024-05-16

申请号：US18479327

申请日：2023-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TSUCHIYAMA ,  Tatsuaki TSUKUDA

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48229 ,  H01L2224/48245 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83095 ,  H01L2224/92147 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

Abstract: A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.

公开(公告)号：US20240120354A1

公开(公告)日：2024-04-11

申请号：US18371258

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Kyong Soon CHO

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/14621 ,  H01L27/14685 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L27/14627 ,  H01L27/1464 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06515 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/0665

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a transparent substrate on the semiconductor chip, a dam structure between the semiconductor chip and the transparent substrate, a dummy pad on a lower side of the dam structure and to which no wiring is connected, a planarization film extending along an upper surface of the semiconductor chip and a passivation film on the planarization film, wherein the planarization film is spaced apart from the dam structure.

公开(公告)号：US20240096387A1

公开(公告)日：2024-03-21

申请号：US18460413

申请日：2023-09-01

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US11935818B2

公开(公告)日：2024-03-19

申请号：US17328933

申请日：2021-05-24

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/4889 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/85455 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20755

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US11881398B2

公开(公告)日：2024-01-23

申请号：US17661890

申请日：2022-05-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. Grivna ,  Stephen St. Germain

IPC: H01L21/02 ,  H01L21/48 ,  H01L21/78 ,  H01L23/14 ,  H01L23/15 ,  H01L23/495 ,  H01L23/498 ,  H01L29/20

CPC classification number: H01L21/02381 ,  H01L21/0254 ,  H01L21/4825 ,  H01L21/78 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49562 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L29/2003 ,  H01L2224/48247 ,  H01L2224/49171

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

公开(公告)号：US20240014164A1

公开(公告)日：2024-01-11

申请号：US18344927

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOOYOUNG OH

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00 ,  H01L23/498

CPC classification number: H01L24/32 ,  H01L24/83 ,  H01L24/30 ,  H01L24/48 ,  H01L24/49 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657 ,  H01L24/73 ,  H01L24/33 ,  H01L25/18 ,  H10B80/00 ,  H01L25/0652 ,  H01L23/49838 ,  H01L2224/83193 ,  H01L2224/83862 ,  H01L2224/32225 ,  H01L2224/3003 ,  H01L2224/3201 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73215 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06565

Abstract: A semiconductor package includes a package substrate, where a plurality of bonding pads are arranged on an upper surface of the package substrate; a semiconductor chip mounted on the upper surface of the package substrate, where a plurality of chip pads are arranged on an upper surface of the semiconductor chip; a first adhesive film attached to a lower surface of the semiconductor chip, wherein the first adhesive film having a first area corresponding to an area of the semiconductor chip; a second adhesive film attached to the upper surface of the package substrate, where the second adhesive film is joined to the first adhesive film, and the second adhesive film has a second area larger than the first area; a plurality of bonding wires; and a molding portion disposed on the upper surface of the package substrate.

公开(公告)号：US11854946B2

公开(公告)日：2023-12-26

申请号：US17864064

申请日：2022-07-13

Applicant: KIOXIA CORPORATION

Inventor： Isao Ozawa

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/00

CPC classification number: H01L23/495 ,  H01L23/28 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/49 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49171 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

公开(公告)号：US20230402352A1

公开(公告)日：2023-12-14

申请号：US18318893

申请日：2023-05-17

Applicant: TDK CORPORATION

Inventor： Kazuma YAMAWAKI ,  Hiraku HIRABAYASHI

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49565 ,  H01L24/48 ,  H01L24/49 ,  H01L23/4952 ,  H01L2224/48245 ,  H01L2224/49171 ,  H01L2224/48257

Abstract: A lead frame includes a die pad, a plurality of leads, and a frame member. The frame member includes a first connection bar extending in a first direction and a second connection bar extending in a second direction. The die pad is connected to the second connection bar. The plurality of leads include a plurality of first leads connected to the first connection bar and a plurality of second leads connected to the second connection bar. The number of the plurality of second leads is smaller than the number of the plurality of first leads. Each of the plurality of second leads is connected to one corresponding first lead of the plurality of first leads.

公开(公告)号：US11830845B2

公开(公告)日：2023-11-28

申请号：US17867554

申请日：2022-07-18

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L24/18 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L21/56 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4824 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.