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公开(公告)号：US20220100657A1
公开(公告)日：2022-03-31
申请号：US17549397
申请日：2021-12-13
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
IPC: G06F12/0806 , G06F9/38 , G06F13/36
Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.
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公开(公告)号：US11275587B2
公开(公告)日：2022-03-15
申请号：US16028840
申请日：2018-07-06
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
Abstract: A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.
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公开(公告)号：US11194582B2
公开(公告)日：2021-12-07
申请号：US16528489
申请日：2019-07-31
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
IPC: G06F9/38 , G06F12/0891 , G06F12/0811 , G06F13/20 , G06F12/0831
Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.
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公开(公告)号：US11182507B2
公开(公告)日：2021-11-23
申请号：US16520299
申请日：2019-07-23
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
IPC: G06F21/62
Abstract: Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.
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公开(公告)号：US20210294754A1
公开(公告)日：2021-09-23
申请号：US17341988
申请日：2021-06-08
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a secure zone configured to store keys and an unscrambled zone configured to operate on unscrambled data. The processor can convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data. Another processor may also be coupled with the memory, but can be prevented from accessing the unscrambled data in the unscrambled zone.
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Patent Agency Ranking
公开(公告)号：US11010288B2
公开(公告)日：2021-05-18
申请号：US16528483
申请日：2019-07-31
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
Abstract: A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.
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公开(公告)号：US20210034369A1
公开(公告)日：2021-02-04
申请号：US16528489
申请日：2019-07-31
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
IPC: G06F9/38 , G06F12/0891 , G06F12/0831 , G06F13/20 , G06F12/0811
Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.
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公开(公告)号：US20200183699A1
公开(公告)日：2020-06-11
申请号：US16210609
申请日：2018-12-05
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
Abstract: Methods, systems, and apparatuses related to re-order buffers and for protection from timing-based security attacks are described. A processor may have functional units configured to execute instructions out of order, a re-order buffer configured to buffer the execution results of instructions for output in order, and a controller configured to randomize data timing in the re-order buffer. For example, the controller can make random adjustments to the capacity of the re-order buffer in buffering and/or sorting execution results and thus randomize data timing in the re-order buffer.
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公开(公告)号：US20200074094A1
公开(公告)日：2020-03-05
申请号：US16520299
申请日：2019-07-23
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
IPC: G06F21/62
Abstract: Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.
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公开(公告)号：US20200073827A1
公开(公告)日：2020-03-05
申请号：US16520298
申请日：2019-07-23
Applicant: Micron Technology, Inc.
Inventor： Steven Jeffrey Wallach
Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.
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