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    IN-MEMORY HASH ENTRIES AND HASHES USED TO IMPROVE KEY SEARCH OPERATIONS FOR KEYS OF A KEY VALUE STORE
    2.
    发明公开
    IN-MEMORY HASH ENTRIES AND HASHES USED TO IMPROVE KEY SEARCH OPERATIONS FOR KEYS OF A KEY VALUE STORE 审中-公开

    公开(公告)号：US20230350810A1

    公开(公告)日：2023-11-02

    申请号：US17732098

    申请日：2022-04-28

    申请人： NetApp Inc.

    发明人： Anil Paul Thoppil ,  Wei Sun ,  Meera Odugoudar ,  Szu-Wen Kuo ,  Santhosh Selvaraj

    IPC分类号： G06F12/1018

    CPC分类号： G06F12/1018

    摘要： Techniques are provided for implementing a hash building process and an append hash building process. The hash building process builds in-memory hash entries for bins of keys stored within sorted logs of a log structured merge tree used to store keys of a key-value store. The in-memory hash entries can be used to identify the starting locations of bins of keys within the log structured merge tree so that a key within a bin can be searched for from the starting location of the bin as opposed to having to search the entire log structured merge tree. The append hash building process builds two hashes that can be used to more efficiently locate keys and/or ranges of keys within an unsorted append log that would otherwise require a time consuming binary search of the entire append log.

    Computation and storage of object identity hash values
    3.
    发明授权
    Computation and storage of object identity hash values 有权

    公开(公告)号：US11755373B2

    公开(公告)日：2023-09-12

    申请号：US17065354

    申请日：2020-10-07

    申请人： Oracle International Corporation

    发明人： John Robert Rose ,  Mikael Vidstedt ,  Erik Österlund

    IPC分类号： G06F9/50 ,  G06F9/54 ,  G06F12/02 ,  G06F12/1018 ,  G06F9/30

    CPC分类号： G06F9/5016 ,  G06F9/3009 ,  G06F9/544 ,  G06F12/0238 ,  G06F12/0253 ,  G06F12/1018

    摘要： Techniques for computing and storing object identity hash values are disclosed. In some embodiments, a runtime system generates a value, such as a nonce, that is unique to a particular allocation region within memory. The runtime system may mix the value with one or more seed values that are associated with one or more respective objects stored in the allocation region. The runtime system may obtain object identifiers for the respective objects by applying a hash function to the result of mixing the seed value with at least the value associated with the allocation region. Conditioning operations may also be applied before, during or after the mixing operations to make the values appear more random. The nonce value may be changed from time to time, such as when memory is recycled in the allocation region, to reduce the risk of hash collisions.

    Digital device for performing booting process and control method therefor
    8.
    发明授权
    Digital device for performing booting process and control method therefor 有权

    公开(公告)号：US11537404B2

    公开(公告)日：2022-12-27

    申请号：US17415471

    申请日：2019-05-29

    申请人： LG ELECTRONICS INC.

    发明人： Kyungsik Lee ,  Kunsu Kim ,  Changyun Jeong ,  Seungho Park

    IPC分类号： G06F9/4401 ,  G06F12/1018

    摘要： The present specification discloses a digital device for performing a hibernation booting process and a control method therefor. Here, the digital device according to an embodiment of the present invention comprises: a first memory; a second memory storing a snapshot image generated on the basis of pieces of page data of the first memory; and a control unit for generating the snapshot image, wherein the control unit primarily deduplicates duplicated page data in the first memory and selectively secondarily deduplicates duplicated page data by comparing the duplicated page data with the snapshot image prestored in the second memory, wherein data fragmentation is minimized through the secondary deduplication step.

    Memory system and method of operating the same
    9.
    发明授权
    Memory system and method of operating the same 有权

    公开(公告)号：US11468119B2

    公开(公告)日：2022-10-11

    申请号：US16930898

    申请日：2020-07-16

    申请人： SK hynix Inc.

    发明人： Dong Sop Lee

    IPC分类号： G06F16/901 ,  G06F12/1018 ,  G11C8/04 ,  G11C7/22 ,  G11C7/10 ,  G11C16/30 ,  G11C16/08

    摘要： A memory system includes a memory device configured to store data, and a memory controller configured to perform communication between a host and the memory device and to control the memory device such that, during an operation of programming sequential data, a hash value is generated from logical block addresses of a memory area, to which the sequential data is to be written, and the hash value is stored and such that, during an operation of reading the sequential data, the sequential data is read from the memory area based on the hash value.

    Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information
    10.
    发明授权
    Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information 有权

    公开(公告)号：US11334488B2

    公开(公告)日：2022-05-17

    申请号：US16898872

    申请日：2020-06-11

    申请人： Microsoft Technology Licensing, LLC

    发明人： Rami Mohammad Al Sheikh ,  Arthur Perais ,  Michael Scott McIlvaine

    IPC分类号： G06F12/0871 ,  G06F12/0855 ,  G06F12/0895 ,  G06F12/1018 ,  G06F12/121

    摘要： A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.