公开(公告)号：US4218876A

公开(公告)日：1980-08-26

申请号：US854214

申请日：1977-11-23

申请人： Shintarou Hashimoto ,  Hirohide Nakagawa ,  Toshio Nishimura

发明人： Shintarou Hashimoto ,  Hirohide Nakagawa ,  Toshio Nishimura

IPC分类号： G04G9/00 ,  G04G99/00 ,  G06F1/04 ,  G06F1/32 ,  G06F15/02 ,  H02J1/00 ,  G06F1/00 ,  G04C23/00

CPC分类号： G04G99/006 ,  G04G9/007 ,  G06F1/3228

摘要： A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.

摘要翻译： 在LSI半导体芯片上实现的组合计时器和计算机包括：发生器级，用于产生可通过修改基本时钟信号获得的基本时钟信号和系统时钟信号;以及处理器级，响应于提供系统时钟信号以执行 计时器模式和计算器模式所需的操作。 基本时钟信号也被修改，以产生在计时器模式下有用的第二个信号。 该发生器在生成第二信号时向处理器单元提供系统时钟信号。 在完成处理器单元的操作之后，时钟控制电路防止处理器单元被提供系统时钟信号。