公开(公告)号：US12117886B2

公开(公告)日：2024-10-15

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US12117882B2

公开(公告)日：2024-10-15

申请号：US18184164

申请日：2023-03-15

Applicant: Hamilton Sundstrand Corporation

Inventor： Balaji Krishnakumar

IPC: G06F1/3228 ,  G06F9/48

CPC classification number: G06F1/3228 ,  G06F9/4887

Abstract: A system having: a processor, wherein the processor is configured for executing a process of reducing power consumption that includes executing a first task over a first plurality of timeslots and a second task over a second plurality of timeslots, and wherein the processor is configured to: execute a real-time operating system (RTOS) process; determine that the first task is complete during a first timeslot of the first plurality of timeslots; and enter a low power mode for a reminder of the first timeslot upon determining that there is enough time to enter a low power mode during the first timeslot and a next timeslot is allocated to the first task, otherwise perform a dead-wait for the reminder of the first timeslot.

公开(公告)号：US20240319781A1

公开(公告)日：2024-09-26

申请号：US18189993

申请日：2023-03-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

公开(公告)号：US20240302878A1

公开(公告)日：2024-09-12

申请号：US18182088

申请日：2023-03-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mantej Singh Gill ,  Dhamodhran Sathyanarayanamurthy ,  Madhusoodhana Chari Sesha ,  Arun Mahendran

IPC: G06F1/18 ,  G06F1/3228

CPC classification number: G06F1/189 ,  G06F1/3228

Abstract: Systems and methods are provided for compressing a time-series dataset from a monitored device into a compressed dataset representation. Using an unsupervised machine learning model, the system may group a contiguous set of datapoints of the time-series dataset and group, using a distance algorithm, the first cluster to a first motif. Many motifs can be generated to identify different data signatures in the time-series dataset. The plurality of motifs can be used to generate a data definition, motif sequence graph, directed graph, or other combinations of datapoints. These datapoints can be combined through a summation process with other datapoints generated by a second machine learning model. The output of the summation process can be used to forecast device usage of a monitored device in a data center.

公开(公告)号：US12086000B1

公开(公告)日：2024-09-10

申请号：US18182088

申请日：2023-03-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mantej Singh Gill ,  Dhamodhran Sathyanarayanamurthy ,  Madhusoodhana Chari Sesha ,  Arun Mahendran

IPC: G06F1/18 ,  G06F1/3228

CPC classification number: G06F1/189 ,  G06F1/3228

Abstract: Systems and methods are provided for compressing a time-series dataset from a monitored device into a compressed dataset representation. Using an unsupervised machine learning model, the system may group a contiguous set of datapoints of the time-series dataset and group, using a distance algorithm, the first cluster to a first motif. Many motifs can be generated to identify different data signatures in the time-series dataset. The plurality of motifs can be used to generate a data definition, motif sequence graph, directed graph, or other combinations of datapoints. These datapoints can be combined through a summation process with other datapoints generated by a second machine learning model. The output of the summation process can be used to forecast device usage of a monitored device in a data center.

公开(公告)号：US20240241561A1

公开(公告)日：2024-07-18

申请号：US18622481

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl D. Wulcan ,  Tal Kuzi ,  Inder M. Sodhi ,  Achmed R. Zahir ,  Ilya Granovsky ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.

公开(公告)号：US12032426B2

公开(公告)日：2024-07-09

申请号：US17891893

申请日：2022-08-19

Applicant: QUALCOMM INCORPORATED

Inventor： Karthik Rangaraju ,  Sumit Gemini ,  Nikhil Kumar Kansal ,  Nirav Narendra Desai ,  Venkata Biswanath Devarasetty ,  Lakshmi Narayana Panuku ,  Venkatesh Ravipati

IPC: G06F1/3228 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3209 ,  G06F9/50 ,  H04M3/22

CPC classification number: G06F1/3228 ,  G06F9/5033 ,  H04M3/2227 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3209

Abstract: Systems, methods and computer-readable mediums may be used in portable computing devices (PCDs) for dynamically allocating system resources in a way that prevents or lessens degradation of power and performance KPIs while also avoiding temperature increases in the PCD that can create unpleasant user experiences. A smart resource allocation framework (SRAF) is triggered when a call is received or placed. Once triggered, the SRAF framework monitors a preselected set of state conditions to determine whether or not to place the wireless modem in a modem power-performance (Mod. Pow.-Perf) mode. If it determines that modem is to be placed in the Mod. Pow.-Perf. mode, a Mod. Pow.-Perf. process is performed dynamically allocates system resources and preferably also triggers a thermal framework that performs power reduction in one or more non-modem processing cores.

公开(公告)号：US12026035B2

公开(公告)日：2024-07-02

申请号：US17957021

申请日：2022-09-30

Applicant: BULL SAS

Inventor： Damien Berton

IPC: G06F1/3296 ,  G06F1/26 ,  G06F1/3228

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/26 ,  Y02D10/00

Abstract: A computing system for adjusting voltage regulation including a main processing module, a secondary processing module that executes requested computation tasks, and a voltage regulation module connected to the secondary processing module that regulates its output voltage according to a regulation law depending on at least one regulation parameter. The system also includes a first digital bus that transfers requested computation tasks from the main processing module to the secondary processing module and transfers results of the requested computation tasks from the secondary processing module to the main processing module. The system also includes a second digital bus that transfers regulation parameters from the main processing module to the voltage regulation module.

公开(公告)号：US12019500B2

公开(公告)日：2024-06-25

申请号：US17839402

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Chung ,  Seunghun Choi

IPC: G06F1/3296 ,  G06F1/20 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F9/30083 ,  G06F9/3836 ,  G06F9/4893 ,  G06F1/206 ,  Y02D10/00

Abstract: An integrated circuit includes; a core configured to process an instruction in accordance with a voltage-frequency level, an instruction complexity calculation circuit configured to calculate an instruction complexity for at least one instruction to-be-processed after a reference time in relation to heating information related to the core acquired before the reference time, wherein the instruction complexity calculation circuit is further configured to generate a control signal corresponding to the instruction complexity, and a dynamic voltage and frequency scaling (DVFS) controller configured to adjust the voltage-frequency level after the reference time in response to the control signal.

公开(公告)号：US11961513B2

公开(公告)日：2024-04-16

申请号：US17388845

申请日：2021-07-29

Applicant: Massachusetts Institute of Technology

Inventor： Michael R. Price ,  James R. Glass ,  Anantha P. Chandrakasan

IPC: G10L15/16 ,  G06F1/3228 ,  G06N3/063 ,  G10L15/06 ,  G10L15/14 ,  G10L15/28 ,  G10L19/035 ,  G10L25/90

CPC classification number: G10L15/16 ,  G06F1/3228 ,  G06N3/063 ,  G10L15/063 ,  G10L15/14 ,  G10L15/142 ,  G10L15/285 ,  G10L19/035 ,  G10L25/90 ,  G10L2015/0633

Abstract: A decoder includes a feature extraction circuit for calculating one or more feature vectors. An acoustic model circuit is coupled to receive one or more feature vectors from and assign one or more likelihood values to the one or more feature vectors. A memory architecture that utilizes on-chip state lattices and an off-chip memory for storing states of transition of the decoder is used to reduce reading and writing to the off-chip memory. The on-chip state lattice is populated with at least one of the states of transition stored in the off-chip memory. An on-chip word is generated from a snapshot from the on-chip state lattice. The on-chip state lattice and the on-chip word lattice act as an on-chip cache to reduce reading and writing to the off-chip memory.