公开(公告)号：US20060120194A1

公开(公告)日：2006-06-08

申请号：US11336751

申请日：2006-01-20

申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

IPC分类号： G11C7/00

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

公开(公告)号：US20060063331A1

公开(公告)日：2006-03-23

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

公开(公告)号：US06936885B2

公开(公告)日：2005-08-30

申请号：US10921656

申请日：2004-08-19

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11524

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

公开(公告)号：US06818510B2

公开(公告)日：2004-11-16

申请号：US10704285

申请日：2003-11-06

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

公开(公告)号：US06583478B2

公开(公告)日：2003-06-24

申请号：US09948201

申请日：2001-09-06

申请人： Sung-Hoi Hur

发明人： Sung-Hoi Hur

IPC分类号： H01L2976

CPC分类号： H01L27/0629 ,  H01L21/76895 ,  H01L27/115 ,  H01L28/40

摘要： A semiconductor transfer circuit and a structure thereof are provided. The transfer circuit and the structure thereof include a stack gate MOS transistor having first and second gate electrodes that are sequentially stacked and a control MOS transistor connected to the stack gate MOS transistor. A drain of the control MOS transistor is connected to the first gate electrode.