Timing controller, clock reset method, and display panel

    公开(公告)号:US11804159B2

    公开(公告)日:2023-10-31

    申请号:US17434005

    申请日:2021-05-31

    Inventor: Jinfeng Liu

    CPC classification number: G09G3/20 G09G2310/08 G09G2330/12

    Abstract: A timing controller, a clock reset method, and a display panel are provided. When an abnormal working condition occurs in a transition stage of recovering a reset control signal from a jumping state to an initial state, the problem that a clock of the timing controller cannot be synchronized can be avoided when a processing module cannot normally output a clock reset pulse signal and a clock data recovering module cannot normally recover the clock of the timing controller because the reset control signal is in the jumping state. Reliability of the timing controller is increased.

    Liquid crystal display backlight module controlling method and controlling device thereof

    公开(公告)号:US11741912B2

    公开(公告)日:2023-08-29

    申请号:US17255009

    申请日:2020-12-18

    CPC classification number: G09G3/3426

    Abstract: A liquid crystal display backlight module controlling method and a controlling device thereof disclosed in the present invention includes a programmable logic gate array board extracting backlight information from an image signal. Calculation of local dimming is performed by the programmable logic gate array board, a calculation buffer for local dimming calculation is sufficient, which can increase liquid crystal display backlight divisions. Furthermore, the present invention employs a row signal and a column signal to control and switch on light emitting diodes in the backlight light board, which can achieve the cost lowering effect.

    TIMING CONTROLLER, CLOCK RESET METHOD, AND DISPLAY PANEL

    公开(公告)号:US20230138499A1

    公开(公告)日:2023-05-04

    申请号:US17434005

    申请日:2021-05-31

    Inventor: Jinfeng Liu

    Abstract: A timing controller, a clock reset method, and a display panel are provided. When an abnormal working condition occurs in a transition stage of recovering a reset control signal from a jumping state to an initial state, the problem that a clock of the timing controller cannot be synchronized can be avoided when a processing module cannot normally output a clock reset pulse signal and a clock data recovering module cannot normally recover the clock of the timing controller because the reset control signal is in the jumping state. Reliability of the timing controller is increased.

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