公开(公告)号：US20210043726A1

公开(公告)日：2021-02-11

申请号：US17081117

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/06 ,  H01L21/76 ,  H01L29/20 ,  H01L29/10 ,  H01L21/761 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/8234

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.

公开(公告)号：US20200083324A1

公开(公告)日：2020-03-12

申请号：US16683604

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761 ,  H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L29/10 ,  H01L21/8252

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a channel layer disposed over a substrate and including a first material. An active layer is over the channel layer and includes a second material different than the first material. An isolation structure has a horizontally extending segment that is below the channel layer and one or more vertically extending segments that are directly over the horizontally extending segment. One or more contacts extend through the channel layer and the active layer to contact the one or more vertically extending segments.

公开(公告)号：US10522618B2

公开(公告)日：2019-12-31

申请号：US16382571

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L21/76 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/761 ,  H01L29/778

Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistor includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.

公开(公告)号：US20190237539A1

公开(公告)日：2019-08-01

申请号：US16382571

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/06 ,  H01L29/778 ,  H01L21/761 ,  H01L29/20 ,  H01L29/66 ,  H01L21/76

CPC classification number: H01L29/0646 ,  H01L21/7605 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.

公开(公告)号：US20190081137A1

公开(公告)日：2019-03-14

申请号：US15703084

申请日：2017-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.

公开(公告)号：US10068976B2

公开(公告)日：2018-09-04

申请号：US15215625

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Man-Ho Kwan ,  Kuei-Ming Chen ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai

IPC: H01L29/15 ,  H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8252

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.