公开(公告)号：US11855199B2

公开(公告)日：2023-12-26

申请号：US17083715

申请日：2020-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Pravanshu Mohanta ,  Ching-Yu Chen ,  Jiang-He Xie ,  Yu-Shine Lin

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

公开(公告)号：US11522067B2

公开(公告)日：2022-12-06

申请号：US17225482

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L21/768 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

公开(公告)号：US11715792B2

公开(公告)日：2023-08-01

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US10068976B2

公开(公告)日：2018-09-04

申请号：US15215625

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Man-Ho Kwan ,  Kuei-Ming Chen ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai

IPC: H01L29/15 ,  H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8252

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

公开(公告)号：US20210242337A1

公开(公告)日：2021-08-05

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US20210226040A1

公开(公告)日：2021-07-22

申请号：US17225482

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L21/768 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

公开(公告)号：US20180026106A1

公开(公告)日：2018-01-25

申请号：US15215625

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chia-Ling Yeh ,  Man-Ho Kwan ,  Kuei-Ming Chen ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai

IPC: H01L29/40 ,  H01L29/205 ,  H01L21/8252 ,  H01L29/66 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.