公开(公告)号：US20120218626A1

公开(公告)日：2012-08-30

申请号：US13503514

申请日：2010-10-08

申请人： Satoru Hamada ,  Shoji Takeshige ,  Keiji Kashima ,  Takashi Kuroda

发明人： Satoru Hamada ,  Shoji Takeshige ,  Keiji Kashima ,  Takashi Kuroda

IPC分类号： G02B5/30

CPC分类号： G02B5/30 ,  G02B5/208 ,  G02B5/26

摘要： Disclosed is an infrared-ray reflective member which efficiently reflects infrared rays (heat rays) contained in sunlight while transmitting visible light rays. The infrared-ray reflective member has an infrared-ray reflective layer having a selective reflection layer for reflecting infrared rays of a right-circularly polarized light component or a left-circularly polarized light component, and the infrared-ray reflective layer has a first reflection band corresponding to a first radiant energy band containing a peak located closest to the short-wavelength side of the infrared range of the spectrum of sunlight on earth, and when the maximum reflectance in the first reflection band is determined at R1 and a wavelength in the short-wavelength side for allowing half-value reflectance of the R1 is determined at λ1, the λ1 is 900 nm to 1010 nm.

摘要翻译： 公开了一种红外线反射构件，其在透射可见光的同时有效地反射包含在太阳光中的红外线（热线）。 红外线反射构件具有红外线反射层，其具有用于反射右圆偏振光分量或左圆偏振光分量的红外线的选择反射层，并且红外线反射层具有第一反射 对应于包含最靠近地球上太阳光谱的红外范围的短波长侧的峰的第一辐射能带，并且当在第一反射带中的最大反射率在R1和波长 在λ1处确定用于允许R1的半值反射率的短波长侧，λ1为900nm至1010nm。

公开(公告)号：US07530009B2

公开(公告)日：2009-05-05

申请号：US11530195

申请日：2006-09-08

申请人： Katsuhiko Katoh ,  Takashi Kuroda ,  Hiroshi Uchiike ,  Yasuhiro Takase

发明人： Katsuhiko Katoh ,  Takashi Kuroda ,  Hiroshi Uchiike ,  Yasuhiro Takase

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B2220/2516

摘要： A data storage device comprising a disk storage medium containing user data in a plurality of sectors wherein each of the plurality of sectors comprises a subdivision of a track, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during the reading process. The error correcting means comprises a syndrome generator for generating syndromes on the basis of the user data, a Euclid circuit, a chien search circuit and a verification circuit, and makes the error correction using a first error correcting code appended to each of a plurality of sectors and a second error correcting code appended to said sector for every block composed of a predetermined number of sectors.

摘要翻译： 一种数据存储装置，包括：磁盘存储介质，其包含多个扇区中的用户数据，其中所述多个扇区中的每一个包括磁道的细分，写入或读取用户数据的磁头以及用于校正发生的错误的纠错装置 在读取过程中的用户数据。 误差校正装置包括用于基于用户数据产生校正子的校正子发生器，欧几里德电路，检索电路和验证电路，并且使用附加到多个 扇区和由预定数量的扇区组成的每个块附加到所述扇区的第二纠错码。

公开(公告)号：US07480188B2

公开(公告)日：2009-01-20

申请号：US11734749

申请日：2007-04-12

申请人： Kazuhiro Nakamuta ,  Iwao Honda ,  Takashi Kuroda

发明人： Kazuhiro Nakamuta ,  Iwao Honda ,  Takashi Kuroda

IPC分类号： G11C7/10

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/06

摘要： A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored at an address identified by the address information at a timing of the clock signal changing from one level to the other level in accordance with the read command, the memory access apparatus comprising: an address information output unit that outputs the address information and the read command at a first timing of the clock signal changing from the one level to the other level; and a read data storage unit that stores data output from the memory at a second timing after the first timing of the clock signal changing from the one level to the other level, the read data storage unit storing the data at a third timing after the second timing of the clock signal changing from the one level to the other level.

摘要翻译： 从存储器读取数据的存储器访问装置，包括输入地址信息的终端的存储器，输入了以预定周期改变的时钟信号的终端，读取命令被输入的终端，以及终端 根据读取命令，在时钟信号从一个电平变化到另一个电平的定时，输出存储在由地址信息识别的地址的数据，该存储器访问装置包括：地址信息输出单元，其输出地址信息 以及所述读取命令在所述时钟信号从所述一个级别改变到另一个级别的第一定时; 以及读取数据存储单元，其在时钟信号从一个电平变化到另一个电平的第一定时之后的第二定时存储从存储器输出的数据，读取数据存储单元在第二时间之后的第三定时存储数据 时钟信号从一个电平变化到另一个电平的时序。

公开(公告)号：US07409607B2

公开(公告)日：2008-08-05

申请号：US11279204

申请日：2006-04-10

申请人： Takashi Kuroda

发明人： Takashi Kuroda

IPC分类号： G11C29/00

CPC分类号： G06F12/0215

摘要： A memory address generating apparatus comprising an address converting circuit, after setting a first setting region storing substitution source data and a second setting region storing substitution destination data that are a substitution target of the substitution source data in an address space provided by the memory, if a specified address specified by the processor as the access destination to the memory is included between a first beginning address and an end address of the first setting region, changing the specified address to a substitution destination address generated by adding a difference between the specified address and the first beginning address to a second beginning address of the second setting region.

摘要翻译： 一种存储器地址产生装置，包括地址转换电路，在存储替代源数据的第一设置区域和存储替换源数据的替代目标数据的存储在由存储器提供的地址空间中的第二设置区域之后，如果 由处理器指定为存储器的访问目的地的指定地址包括在第一设置区域的第一起始地址和结束地址之间，将指定的地址改变为通过将指定地址和 第一开始地址到第二设置区域的第二起始地址。

公开(公告)号：US20070147137A1

公开(公告)日：2007-06-28

申请号：US11614793

申请日：2006-12-21

申请人： Takashi Kuroda ,  Iwao Honda ,  Noriyuki Tomita ,  Hideki Ohashi

发明人： Takashi Kuroda ,  Iwao Honda ,  Noriyuki Tomita ,  Hideki Ohashi

IPC分类号： G11C7/10

CPC分类号： G06F12/04

摘要： A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.

摘要翻译： 一种存储器控制电路，其控制具有k比特宽度的m（= L / k）个存储器（第一至第m个存储器），m个存储器存储具有k的整数倍的数据宽度（D比特）的数据 该位电路包括：地址输入电路，其基于作为预定的j位的起始位置指定地址，确定在m个存储器中存储数据的前k位的存储器（第n个存储器） 指示数据的存储目的地的A位地址，并且向第n至第m存储器输入用于指定数据的存储目的地的第一指定地址，第一指定地址是A位地址的Aj位，其中 是没有其预定j比特的A比特地址，并且向第一到第（n-1）个存储器输入通过将一个加到第一指定地址而获得的第二指定地址; 数据输入电路，按照第n〜第m个存储器和第1〜第（n-1）个存储器的顺序，分别输入将数据分割成k位数据而得到的多条划分数据 在起始位置指定地址; 数据输出电路，按照第n至第m个存储器和第1至第（n-1）个存储器的顺序从存储器分别读取多个划分的数据，对应于数据宽度的存储器的数量 并根据开始位置指定地址输出读取的多条分割数据作为数据; 以及存储器选择电路，其基于开始位置指定地址和数据宽度，以第n至第m个存储器和第一至第（n-1）个存储器的顺序，使D / k存储器可读/可写 数据。

公开(公告)号：US20070146194A1

公开(公告)日：2007-06-28

申请号：US11614821

申请日：2006-12-21

申请人： Iwao Honda ,  Hideki Ohashi ,  Takashi Kuroda ,  Noriyuki Tomita

发明人： Iwao Honda ,  Hideki Ohashi ,  Takashi Kuroda ,  Noriyuki Tomita

IPC分类号： G08C19/12

CPC分类号： H04L1/0043

摘要： An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.

摘要翻译： 公开了一种编码电路，其包括：存储用于编码的n比特数据的用于编码的数据存储寄存器; 数据计算存储寄存器，其存储用于通过移位用于编码的数据而生成的用于计算的m位数据; 移位器，用于移位存储在数据编码存储寄存器中的用于编码的数据，并将移位的数据移位并输入到计算数据存储寄存器; 存储指示用于执行编码的第一系数的m位第一系数数据的第一系数寄存器; 输入存储在计算用数据存储寄存器中的用于计算的数据的第一逻辑电路和存储在第一系数寄存器中的第一系数数据，并输出用于计算的数据的每个位的逻辑积，并且第一系数 数据; 以及第二逻辑电路，其输入从第一逻辑电路输出的m位数据，并输出作为编码数据的m位数据的异或逻辑和。

公开(公告)号：US20070042189A1

公开(公告)日：2007-02-22

申请号：US11504485

申请日：2006-08-15

申请人： Kenji Shirai ,  Keiji Kashima ,  Takashi Kuroda ,  Takeshi Haritani

发明人： Kenji Shirai ,  Keiji Kashima ,  Takashi Kuroda ,  Takeshi Haritani

IPC分类号： B32B9/04

CPC分类号： C09K19/2007 ,  C09K2019/0448 ,  G02B5/3016 ,  G02B5/3083 ,  Y10T428/31504

摘要： A main object of the present invention is to provide a highly reliable retardation film without the problems of peeling off of the retardation layer from the base material or the like generated in the case of forming the retardation layer, capable of easily obtaining an optional retardation value even for a small amount, and capable of improving the adhering property with a hydrophilic film such as a polarizing layer. In order to achieve the above-mentioned object, the present invention provides a retardation film, comprising a polymer film containing a material having refractive index anisotropy, wherein the material having refractive index anisotropy has a concentration gradient in a thickness direction of the polymer film.

摘要翻译： 本发明的主要目的在于提供一种高可靠性的相位差膜，而不会产生相位差层从形成延迟层的情况下所产生的基材等的剥离的问题，能够容易地获得任意的延迟值 甚至少量，并且能够用诸如偏振层的亲水性膜改善粘附性能。 为了实现上述目的，本发明提供了一种延迟膜，其包括含有折射率各向异性的材料的聚合物膜，其中具有折射率各向异性的材料在聚合物膜的厚度方向上具有浓度梯度。

公开(公告)号：US06603621B1

公开(公告)日：2003-08-05

申请号：US09662038

申请日：2000-09-14

申请人： Yuhji Kigami ,  Takashi Kuroda ,  Masayuki Murakami

发明人： Yuhji Kigami ,  Takashi Kuroda ,  Masayuki Murakami

IPC分类号： G11B1512

CPC分类号： G06F3/061 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0676 ,  G11B20/10 ,  G11B20/1217

摘要： A system and method within a hard disk drive for transferring track sector information of a storage disk to a memory device. The system of the present invention includes a disk having multiple tracks, wherein each of the tracks includes at least one sector. The system further includes a memory device for storing sector identification data and user data. A drive data bus is utilized for transferring data between the storage disk and the memory. A controller is utilized to manages read and write operations to and from the storage disk, wherein the controller includes means for selecting either said user data or said sector identification data to be transferred to said memory device.

摘要翻译： 用于将存储盘的轨道扇区信息传送到存储设备的硬盘驱动器内的系统和方法。 本发明的系统包括具有多个磁道的磁盘，其中每个磁道包括至少一个扇区。 该系统还包括用于存储扇区标识数据和用户数据的存储器装置。 驱动数据总线用于在存储盘和存储器之间传送数据。 使用控制器来管理到存储盘和从存储盘的读取和写入操作，其中控制器包括用于选择要传送到所述存储器设备的所述用户数据或所述扇区标识数据的装置。

公开(公告)号：US06178057B1

公开(公告)日：2001-01-23

申请号：US09105687

申请日：1998-06-26

申请人： Takashi Kuroda ,  Yuji Kigami

发明人： Takashi Kuroda ,  Yuji Kigami

IPC分类号： G11B509

CPC分类号： G11B5/012

摘要： To realize simplification of the structure and high reliability in the disk drive. When a position of a target sector on a disk 2 is detected while skipping data sectors including a first region which is written using a first read/write clock (RDWTCLK) and a second region which is written using a second read/write clock, a controller 5b in a HDC 5 presets to a counter 5a an offset value which is based on the length of a sector to be skipped and a difference in the frequency between the first and the second RDWTCLKs and counts the first RDWTCLK fed from a CLK generator 4d of a channel IC 4 to detect the position of the target sector.

摘要翻译： 实现磁盘驱动器的结构简化和高可靠性。 当在跳过包括使用第一读/写时钟（RDWTCLK）写入的第一区域和使用第二读/写时钟写入的第二区域的数据扇区的同时检测到盘2上的目标扇区的位置时， HDC 5中的控制器5b预先计数到计算器5a的偏移值，该偏移值基于要跳过的扇区的长度和第一和第二RDWTCLK之间的频率差，并对从CLK发生器4d馈送的第一RDWTCLK进行计数 通道IC4检测目标扇区的位置。

公开(公告)号：US5181240A

公开(公告)日：1993-01-19

申请号：US696935

申请日：1991-05-08

申请人： Satoshi Sakuragi ,  Takeshi Ikeda ,  Takashi Kuroda

发明人： Satoshi Sakuragi ,  Takeshi Ikeda ,  Takashi Kuroda

IPC分类号： H04M11/00 ,  H04M11/06 ,  H04M19/08

CPC分类号： H04M19/08 ,  H04M11/06

摘要： A data circuit-terminating equipment with a power source device attached thereto comprising a data circuit-terminating device such as a modem system including a power source device for supplying a power extracted from a telephone circuit to the data circuit-terminating device.