Abstract:
A security processor integrated within a system may be securely shut down. The security processor may receive shut down requests, and may determine components and/or subsystems that need be shut down during shut down periods. The security processor may determine when each of the relevant components is ready for shut down. Once the relevant components are shut down, the security processor may itself be shut down, wherein the shut down of the security processor may be performed by stopping the clocking of the security processor. A security error monitor may monitor the system during shut down periods, and the security processor may be powered back on when security breaches and/or threats may be detected via the security error monitor. The security error monitor may be enabled to power on the security processor by reactivating the security processor clock, and the security processor may then power on the system.
Abstract:
A security processor integrated within a system may be securely shut down. The security processor may receive shut down requests, and may determine components and/or subsystems that need be shut down during shut down periods. The security processor may determine when each of the relevant components is ready for shut down. Once the relevant components are shut down, the security processor may itself be shut down, wherein the shut down of the security processor may be performed by stopping the clocking of the security processor. A security error monitor may monitor the system during shut down periods, and the security processor may be powered back on when security breaches and/or threats may be detected via the security error monitor. The security error monitor may be enabled to power on the security processor by reactivating the security processor clock, and the security processor may then power on the system.
Abstract:
Aspects of a method and system for glitch protection in a secure system are provided. In this regard, the output of an on-chip security operation may be combinatorially compared with an expected output of the security operation. Based on the results of the comparison, one or more signals which may control access to one or more on-chip secure functions may be generated. The security operation may, for example, comprise generating a message digest utilizing a SHA and/or modifying a stored value based on an amount of code being executed. The expected output may comprise a single value or range of values. In this regard, a system may, for example, be protected from glitch attacks causing lines-of code to be skipped and or causing enable signals to be forced to an illegitimate value.
Abstract:
In one embodiment, there is presented a method for processing data. The method comprises receiving a plurality of packets, wherein each packet comprises a payload, and wherein the plurality of packets carry video data encoded in accordance with an encoding standard from a plurality of encoding standards; identifying encoding standards encoding the video data carried in the payloads of the plurality of packets; and inserting identifiers that identify the encoding standard encoding the video data carried in the payloads of the plurality of packets into the plurality of packets.
Abstract:
Presented herein are system(s) for demultiplexing, merging, and duplicating packetized elementary stream/program stream/elementary stream data. In one embodiment, there is presented a system for processing data. The system comprises a first circuit and a memory. The first circuit receives transport packets carrying the data. The memory stores data and comprises at least one context. The first circuit maps the data associated with at least one channel to the at least one context.
Abstract:
A method and system are provided for providing data commonality in a programmable transport demultiplexer engine. The method may involve utilizing a hardware assist block to process a portion of an incoming data packet, which may result in a partially processed data packet. The data packet may comprise data in any one of video formats and/or audio formats. A firmware block may then execute a plurality of instructions to process the partially processed data packet. The plurality of instructions may be independent of video and/or audio formats associated with the data packet.