公开(公告)号：US06251723B1

公开(公告)日：2001-06-26

申请号：US09411236

申请日：1999-10-04

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： In a method for manufacturing a semiconductor memory device, a plurality of openings are perforated in an insulating layer formed on first impurity diffusion regions for bit lines and second impurity diffusion regions for capacitors of a semiconductor substrate surrounded by a field insulating layer, and each of the openings corresponds to one of the first impurity diffusion regions and at least two of the second impurity diffusion regions.

摘要翻译： 在制造半导体存储器件的方法中，在由场绝缘层包围的半导体衬底的电容器的位线和第二杂质扩散区域上形成的绝缘层中开有多个开口，并且 所述开口对应于所述第一杂质扩散区域和所述第二杂质扩散区域中的至少两个之一。

公开(公告)号：US06239001B1

公开(公告)日：2001-05-29

申请号：US09005739

申请日：1998-01-12

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L2176

CPC分类号： H01L21/76202 ,  H01L21/76235

摘要： Disclosed is a method for making a semiconductor device where a device region and a device isolation region for electrically isolating between devices are formed on a semiconductor substrate, said device region including a transistor, which has the steps of: forming device isolation film by using polysilicon film or amorphous silicon film as a buffer; and oxidizing the polysilicon film or amorphous film into silicon oxide film and then removing the silicon oxide film after forming the device isolation film.

摘要翻译： 公开了一种制造半导体器件的方法，其中在半导体衬底上形成用于电绝缘的器件区域和器件隔离区域，所述器件区域包括晶体管，其具有以下步骤：通过使用多晶硅形成器件隔离膜 膜或非晶硅膜作为缓冲液; 并将多晶硅膜或非晶膜氧化成氧化硅膜，然后在形成器件隔离膜之后除去氧化硅膜。

公开(公告)号：US6063669A

公开(公告)日：2000-05-16

申请号：US805273

申请日：1997-02-25

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/10876

摘要： A manufacturing method provides a semiconductor device having a trench gate type transistor and a planer type transistor gate electrodes are formed certainly and without increasing the number of photolithography steps. After formation of a gate insulating film, a polysilicon film, and a WSi film for a transistor in a peripheral circuit section, an oxide film is formed on the entire surface of the resultant structure. Subsequently, the oxide film in a trench formation region is selectively removed in a memory cell array section and the oxide film other than a gate electrode formation region is selectively removed in the peripheral circuit section. A silicon substrate is etched using the remaining oxide film as a mask to form a trench in the memory cell array section, and the polysilicon film and the WSi film are etched to form the gate electrode in the peripheral circuit section. Thereafter, a gate insulating film and a gate electrode for a cell transistor are formed in the trench of the memory cell array section.

摘要翻译： 制造方法提供了具有沟槽栅型晶体管的半导体器件，并且不增加光刻步骤的数量确定地形成了平面型晶体管栅电极。 在外围电路部中形成栅绝缘膜，多晶硅膜和晶体管用WSi膜之后，在所得结构的整个表面上形成氧化物膜。 随后，在存储单元阵列部分选择性地去除沟槽形成区域中的氧化物膜，并且在外围电路部分中选择性地去除栅电极形成区域以外的氧化膜。 使用剩余的氧化物膜作为掩模蚀刻硅衬底，以在存储单元阵列部分中形成沟槽，并且在外围电路部分中蚀刻多晶硅膜和WSi膜以形成栅电极。 此后，在存储单元阵列部分的沟槽中形成栅极绝缘膜和用于单元晶体管的栅电极。

公开(公告)号：US5903430A

公开(公告)日：1999-05-11

申请号：US831001

申请日：1997-03-31

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/30

CPC分类号： H01L28/87 ,  H01L27/10814 ,  H01L27/10852

摘要： The present invention provides a capacitor comprising: a semiconductor substrate; an inter-layer insulator formed over the silicon substrate; at least two interconnections formed within the inter-layer insulator, the two interconnections being distanced at a pitch in a lateral direction; a fin-structured storage electrode comprising a vertically extending column portion and a plurality of fins, each of which laterally and radially extends from the vertically extending column portion, the fins being spaced in a vertical direction and the vertically extending column portion extending through the inter-layer insulator to a surface of the semiconductor substrate and also extending upwardly from a surface of the inter-layer insulator, wherein the vertically extending column portion is smaller in diameter within the inter-layer insulator and larger in diameter over the inter-layer insulator; a capacitive insulation film formed on a surface of the fin-structured storage electrode; and an opposite electrode formed on the capacitive insulation film.

摘要翻译： 本发明提供一种电容器，包括：半导体衬底; 形成在所述硅衬底上的层间绝缘体; 形成在所述层间绝缘体内的至少两个互连，所述两个互连以横向方向间距分开; 翅片结构的存储电极，其包括垂直延伸的柱部分和多个翅片，每个翼片从垂直延伸的柱部分横向和径向延伸，翅片在垂直方向上间隔开，并且垂直延伸的柱部分延伸穿过相互之间 层绝缘体到半导体衬底的表面并且还从层间绝缘体的表面向上延伸，其中垂直延伸的柱部分在层间绝缘体内的直径更小并且在层间绝缘体上的直径更大 ; 形成在所述鳍状结构的存储电极的表面上的电容绝缘膜; 以及形成在电容绝缘膜上的相对电极。

公开(公告)号：US5801079A

公开(公告)日：1998-09-01

申请号：US569006

申请日：1995-12-07

申请人： Yoshihiro Takaishi

发明人： Yoshihiro Takaishi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  Y10S148/014

摘要： In a stacked capacitor type semiconductor device, first and second insulating layers are formed on a semiconductor substrate. A capacitor lower electrode layer is formed in an opening formed within the second insulating layer, and is electrically connected via a contact hole of the first insulating layer to an impurity doped region of the semiconductor substrate. A capacitor insulating layer is formed on the capacitor lower electrode layer, and a capacitor upper electrode layer is formed on the capacitor insulating layer.

摘要翻译： 在叠层电容器型半导体器件中，在半导体衬底上形成第一绝缘层和第二绝缘层。 电容器下电极层形成在形成在第二绝缘层内的开口中，并且经由第一绝缘层的接触孔电连接到半导体衬底的杂质掺杂区域。 在电容器下电极层上形成电容器绝缘层，在电容绝缘层上形成电容器上电极层。