公开(公告)号：US07773595B2

公开(公告)日：2010-08-10

申请号：US11855697

申请日：2007-09-14

申请人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

发明人： Malcolm J. Wing ,  Jay B. Patel ,  Jeffrey M. Schroeder

IPC分类号： H04L12/56 ,  H04J1/16

CPC分类号： H04L43/18 ,  H04L69/12 ,  H04L69/22 ,  H04L69/324

摘要： A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.

摘要翻译： 一种用于解析帧的系统，包括被配置为从第一帧识别第一小区的第一小区提取电路（CEC），可操作地连接到第一CEC的第一解析器引擎，其中第一解析器引擎被配置为基于 第一单元和第一转发电路，其可操作地连接到第一解析器引擎并且被配置为转发结果，其中第一CEC，第一解析器引擎和第一转发电路与第一帧解析器单元相关联。

公开(公告)号：US20080132007A1

公开(公告)日：2008-06-05

申请号：US11634039

申请日：2006-12-05

申请人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

发明人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit. Architectures for these integrated circuits can contain a field programmable gate array that is integrated with a mask programmable gate array in a ring structure.

摘要翻译： 本发明提供了用于混合集成电路的结构和用于产生这些混合集成电路的方法，所述混合集成电路既包含现场可编程门阵列，也包含掩模可编程门阵列，这是一种专用集成电路的形式。 用于制造现场可编程和可编程掩模的集成电路的方法包括以下步骤：设计晶片组层和精加工层，其中晶片组层提供多个可选功能块; 制造所述晶片组层; 设计用于所述集成电路的掩模编程互连层，其中所述互连层将所述多个功能块中的选定的互连层与所述晶片库层相互连接; 制造晶片堤层上的互连层; 以及在互连层上制造精加工层以产生集成电路。 这些集成电路的架构可以包含与环形结构中的掩模可编程门阵列集成的现场可编程门阵列。