公开(公告)号：US08629006B2

公开(公告)日：2014-01-14

申请号：US11634039

申请日：2006-12-05

申请人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

发明人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit. Architectures for these integrated circuits can contain a field programmable gate array that is integrated with a mask programmable gate array in a ring structure.

摘要翻译： 本发明提供了用于混合集成电路的结构和用于产生这些混合集成电路的方法，所述混合集成电路既包含现场可编程门阵列，也包含掩模可编程门阵列，这是一种专用集成电路的形式。 用于制造现场可编程和可编程掩模的集成电路的方法包括以下步骤：设计晶片组层和精加工层，其中晶片组层提供多个可选功能块; 制造所述晶片组层; 设计用于所述集成电路的掩模编程互连层，其中所述互连层将所述多个功能块中的选定的互连层与所述晶片库层相互连接; 制造晶片堤层上的互连层; 以及在互连层上制造精加工层以产生集成电路。 这些集成电路的架构可以包含与环形结构中的掩模可编程门阵列集成的现场可编程门阵列。

公开(公告)号：US20080132007A1

公开(公告)日：2008-06-05

申请号：US11634039

申请日：2006-12-05

申请人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

发明人： Steven Winegarden ,  Ronald Nicholson ,  John Jun Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask programmable include the steps of: designing wafer bank layers and finishing layers, where the wafer bank layers provide a plurality of selectable functional blocks; fabricating said wafer bank layers; designing mask programmed interconnect layers for said integrated circuit, where the interconnect layers interconnect selected ones of the plurality of functional blocks from the wafer bank layers; fabricating the interconnect layers on the wafer bank layers; and fabricating the finishing layers on the interconnect layers to produce the integrated circuit. Architectures for these integrated circuits can contain a field programmable gate array that is integrated with a mask programmable gate array in a ring structure.

摘要翻译： 本发明提供了用于混合集成电路的结构和用于产生这些混合集成电路的方法，所述混合集成电路既包含现场可编程门阵列，也包含掩模可编程门阵列，这是一种专用集成电路的形式。 用于制造现场可编程和可编程掩模的集成电路的方法包括以下步骤：设计晶片组层和精加工层，其中晶片组层提供多个可选功能块; 制造所述晶片组层; 设计用于所述集成电路的掩模编程互连层，其中所述互连层将所述多个功能块中的选定的互连层与所述晶片库层相互连接; 制造晶片堤层上的互连层; 以及在互连层上制造精加工层以产生集成电路。 这些集成电路的架构可以包含与环形结构中的掩模可编程门阵列集成的现场可编程门阵列。

公开(公告)号：US07928764B2

公开(公告)日：2011-04-19

申请号：US12375560

申请日：2006-08-31

申请人： John Jun Yu ,  Fungfung Lee ,  Wen Zhou

发明人： John Jun Yu ,  Fungfung Lee ,  Wen Zhou

IPC分类号： H01L25/00 ,  H03K19/173 ,  G11C5/00

CPC分类号： H03K19/17736

摘要： A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.

摘要翻译： 用于逻辑单元阵列的可编程互连网络。 所述互连网络具有以树结构连接的多个开关盒，并提供与其逻辑单元的连接，位于树结构的最底层的开关盒连接到逻辑单元; 所述互连网络还具有外围交换机盒，其中至少一个连接到外部逻辑。 此外，集成电路包括由所述可编程互连网络连接的逻辑单元的FP阵列和掩模可编程（MP）逻辑阵列。

公开(公告)号：US20090261858A1

公开(公告)日：2009-10-22

申请号：US12375560

申请日：2006-08-31

申请人： John Jun Yu ,  Fungfung Lee ,  Wen Zhou

发明人： John Jun Yu ,  Fungfung Lee ,  Wen Zhou

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736

摘要： A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array.

摘要翻译： 用于逻辑单元阵列的可编程互连网络。 所述互连网络具有以树结构连接的多个开关盒，并提供与其逻辑单元的连接，位于树结构的最底层的开关盒连接到逻辑单元; 所述互连网络还具有外围交换机盒，其中至少一个连接到外部逻辑。 此外，集成电路包括由所述可编程互连网络连接的逻辑单元的FP阵列和掩模可编程（MP）逻辑阵列。