公开(公告)号：US11588519B2

公开(公告)日：2023-02-21

申请号：US17475211

申请日：2021-09-14

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Chia Hao Chen ,  Nicolas Cordier

IPC: H04B5/00 ,  H02J50/10 ,  H02J50/80 ,  H02J50/90

Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

公开(公告)号：US20230044794A1

公开(公告)日：2023-02-09

申请号：US17962014

申请日：2022-10-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent BIDAULT

IPC: G06T7/00 ,  G06N3/04

Abstract: A device includes image generation circuitry and convolutional-neural-network circuitry. The image generation circuitry, in operation, generates a digital image representation of a wafer defect map (WDM). The convolutional-neural-network circuitry, in operation, generates a defect classification associated with the WDM based on the digital image representation of the WDM and a data-driven model generated using an artificial wafer defect digital image (AWDI) data set and associating AWDIs with classes of a defined set of classes of wafer defects. A wafer manufacturing process may be controlled based on the classifications of WDMs.

公开(公告)号：US20230019539A1

公开(公告)日：2023-01-19

申请号：US17947461

申请日：2022-09-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: G01K15/00 ,  G01K7/01 ,  G01R19/00

Abstract: Two sets of the DC voltages are determined from among sets of DC voltages. At a first temperature, a first voltage of one of the two sets and a first voltage of the other one of the two sets surround a detection voltage that varies substantially proportionally to temperature. The detection voltage is compared with a second voltage of one of the two sets.

公开(公告)号：US20230019484A1

公开(公告)日：2023-01-19

申请号：US17861329

申请日：2022-07-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lia MASOERO ,  Patrick CALENZO

IPC: H01L27/112

Abstract: A one-time programmable memory cell includes a transistor coupled to a capacitor. The transistor includes at least one first conductive gate element arranged in at least one first trench formed in a semiconductor substrate, and at least one first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.

公开(公告)号：US11533019B2

公开(公告)日：2022-12-20

申请号：US17180752

申请日：2021-02-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Benoit Marchand ,  Hamilton Emmanuel Querino De Carvalho ,  Achraf Dhayni ,  Daniele Mangano

IPC: H04B1/04 ,  H03F3/24 ,  H03B5/36 ,  H03L1/02 ,  H03L7/099 ,  G06F1/10

Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

公开(公告)号：US20220375954A1

公开(公告)日：2022-11-24

申请号：US17747540

申请日：2022-05-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric GAY ,  Abderrezak MARZAKI

IPC: H01L27/11526 ,  H01L27/11521

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

公开(公告)号：US11500767B2

公开(公告)日：2022-11-15

申请号：US16810546

申请日：2020-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Folliot ,  Pierre Demaj

IPC: G06F21/00 ,  G06F12/02

Abstract: In accordance with an embodiment, a method for determining an overall memory size of a global memory area configured to store input data and output data of each layer of a neural network includes: for each current layer of the neural network after a first layer, determining a pair of elementary memory areas based on each preceding elementary memory area associated with a preceding layer, wherein: the two elementary memory areas of the pair of elementary memory areas respectively have two elementary memory sizes, each of the two elementary memory areas are configured to store input data and output data of the current layer of the neural network, the output data is respectively stored in two different locations, and the overall memory size of the global memory area corresponds to a smallest elementary memory size at an output of the last layer of the neural network.

公开(公告)号：US11495275B2

公开(公告)日：2022-11-08

申请号：US17336841

申请日：2021-06-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Eva ,  Jean-Michel Gril-Maffre

IPC: G11C7/22 ,  G06F13/42 ,  G11C7/10 ,  G11C16/34

Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

公开(公告)号：US11454554B2

公开(公告)日：2022-09-27

申请号：US16576377

申请日：2019-09-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: G01K15/00 ,  G01K7/01 ,  G01R19/00

Abstract: Two sets of the DC voltages are determined from among sets of DC voltages. At a first temperature, a first voltage of one of the two sets and a first voltage of the other one of the two sets surround a detection voltage that varies substantially proportionally to temperature. The detection voltage is compared with a second voltage of one of the two sets.

公开(公告)号：US20220283896A1

公开(公告)日：2022-09-08

申请号：US17684198

申请日：2022-03-01

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Albert MARTINEZ ,  Patrick HADDAD

IPC: G06F11/10 ,  G06F11/26 ,  G06F7/58

Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.