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23 条记录 (耗时 0.018 秒)

    Electronic switching device with reduction of leakage currents and corresponding control method
    2.
    发明授权
    Electronic switching device with reduction of leakage currents and corresponding control method 有权

    公开(公告)号：US10230363B2

    公开(公告)日：2019-03-12

    申请号：US15490356

    申请日：2017-04-18

    申请人： STMicroelectronics (Rousset) SAS

    发明人： Bruno Gailhard ,  Michel Cuenca

    IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K3/012 ,  G11C27/02

    摘要： A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

    Method and Device for Controlling a Sample and Hold Circuit
    3.
    发明申请
    Method and Device for Controlling a Sample and Hold Circuit 有权
    用于控制采样和保持电路的方法和装置

    公开(公告)号：US20150155053A1

    公开(公告)日：2015-06-04

    申请号：US14549291

    申请日：2014-11-20

    申请人： STMicroelectronics (Rousset) SAS

    发明人： Bruno Gailhard ,  Yohan Joly

    IPC分类号： G11C27/02

    CPC分类号： G11C27/024 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  H03K3/0231

    摘要： A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

    摘要翻译： 提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。 采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。 至少一个主电流被传送到至少一个辅助电容器。 从至少一个辅助电容器的充电和放电产生初始脉冲信号。 采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

    Method for managing a phase-locked loop and related circuit
    6.
    发明授权
    Method for managing a phase-locked loop and related circuit 有权

    公开(公告)号：US10530374B2

    公开(公告)日：2020-01-07

    申请号：US16289225

    申请日：2019-02-28

    申请人： STMicroelectronics (Rousset) SAS

    发明人： Bruno Gailhard

    IPC分类号： H03L7/10 ,  H03L7/14 ,  H03L7/089 ,  H03L7/099

    摘要： A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.

    Method and device for controlling a sample and hold circuit
    8.
    发明授权
    Method and device for controlling a sample and hold circuit 有权
    用于控制采样和保持电路的方法和装置

    公开(公告)号：US09460808B2

    公开(公告)日：2016-10-04

    申请号：US14549291

    申请日：2014-11-20

    申请人： STMicroelectronics (Rousset) SAS

    发明人： Bruno Gailhard ,  Yohan Joly

    IPC分类号： H03K5/00 ,  G11C27/02 ,  G11C29/50 ,  G11C29/02 ,  H03K3/0231

    CPC分类号： G11C27/024 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  H03K3/0231

    摘要： A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

    摘要翻译： 提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。 采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。 至少一个主电流被传送到至少一个辅助电容器。 从至少一个辅助电容器的充电和放电产生初始脉冲信号。 采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

    Electronic Switching Device with Reduction of Leakage Currents and Corresponding Control Method
    9.
    发明申请
    Electronic Switching Device with Reduction of Leakage Currents and Corresponding Control Method 有权
    减少漏电流的电子开关装置及相应的控制方法

    公开(公告)号：US20150145564A1

    公开(公告)日：2015-05-28

    申请号：US14536122

    申请日：2014-11-07

    申请人： STMicroelectronics (Rousset) SAS

    发明人： Bruno Gailhard ,  Michel Cuenca

    IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K3/012

    CPC分类号： H03K17/161 ,  G11C27/024 ,  H03K3/012 ,  H03K17/6872

    摘要： A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

    摘要翻译： 一种方法用于控制包括具有主MOS晶体管的开关单元的电子器件，所述主MOS晶体管具有衬底，第一导电电极和耦合到输出端子的第二导电电极。 该方法包括以这样的方式控制主晶体管，使其处于导通状态或截止状态，使得当主晶体管处于导通状态时，主晶体管的基板和第一导电电极连接到 输入端子，并且当主晶体管处于截止状态时，主晶体管的第一导电电极与输入端隔离，并且第一偏置电压被施加到第一导电电极，并且第二偏置电压施加到 主晶体管的衬底。

    LDO overshoot protection in a cascaded architecture
    10.
    发明授权
    LDO overshoot protection in a cascaded architecture 有权

    公开(公告)号：US11703897B2

    公开(公告)日：2023-07-18

    申请号：US16810639

    申请日：2020-03-05

    申请人： STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

    发明人： Michel Cuenca ,  Bruno Gailhard ,  Daniele Mangano

    IPC分类号： G05F1/56

    CPC分类号： G05F1/56

    摘要： In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.