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公开(公告)号：US20220005400A1
公开(公告)日：2022-01-06
申请号：US17279478
申请日：2020-05-25
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.
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62.发明申请公开(公告)号：US20210408160A1
公开(公告)日：2021-12-30
申请号：US16963346
申请日：2019-09-27
Inventor： Can Yuan , Yongqian Li , Pan Xu , Zhidong Yuan , Meng Li , Xuehuan Feng , Zehua Ding
IPC: H01L27/32 , G09G3/3225
Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.
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公开(公告)号：US20210407358A1
公开(公告)日：2021-12-30
申请号：US16963444
申请日：2019-10-18
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: A shift register unit includes a first node connection branch, an ON/OFF control circuit and a third node control circuit. A first end of the first node connection branch is electrically connected to first node, and a second end of the first node connection branch is electrically connected to a third node. The first node connection branch is configured to control the first node to be electrically connected to the third node under the control of a potential at the first node. The ON/OFF control circuit is configured to control the third node to be electrically connected to a first voltage end under the control of the potential at the first node. The third node control circuit is configured to reset a potential at the third node under the control of a resetting signal from a resetting end and a potential at a second node.
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公开(公告)号：US11200825B2
公开(公告)日：2021-12-14
申请号：US16767230
申请日：2019-12-16
Inventor： Xuehuan Feng , Yongqian Li , Xing Zhang
Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes a first input sub-circuit to an Nth input sub-circuit and a first output sub-circuit to an Nth output sub-circuit. N is an integer greater than or equal to 2. For n=1, 2, . . . , N, an nth input sub-circuit is electrically coupled to an nth input signal terminal, a first level signal terminal and a pull-up node, and an nth output sub-circuit is electrically coupled to an nth clock signal terminal, the pull-up node and an nth output signal terminal.
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公开(公告)号：US20210335266A1
公开(公告)日：2021-10-28
申请号：US16623653
申请日：2019-05-23
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register unit, a driving method thereof, a gate driver and a display device are provided. The shift register unit includes a first input circuit, an output circuit and a charging enhancement circuit. The first input circuit is configured to charge a first node in response to a first input signal; the output circuit is configured to output, under control of a level of the first node, a shift signal for a row-by-row shift of scanning and a first output signal for driving one row of sub-pixel units in a display panel to perform display scanning; and the charging enhancement circuit is configured to further enhance the level of the first node in response to a charging enhancement signal. The shift register unit may enhance the level of the first node and the reliability of the gate driver and the display device consisted of the shift register unit.
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Patent Agency Ranking
公开(公告)号：US20210233476A1
公开(公告)日：2021-07-29
申请号：US17256049
申请日：2020-02-12
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan , Min He , Haixia Xu
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register unit, a driving method, a gate driving circuit, and a display device are disclosed. The shift register unit includes: a shift circuit, used to output, to a first output end during a first time period, a power control signal, and output the power control signal to a second output end during a second time period; and a signal integrated circuit, used to output the power control signal to a third output end in response to the power control signal and a first output signal, output the power control signal to the third output end in response to the power control signal and a second output signal, and output, to the third output end at times other than the first and second time period in response to the power control signal, the first output signal and the second output signal, a first pull-down power signal.
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公开(公告)号：US20210209987A1
公开(公告)日：2021-07-08
申请号：US16768536
申请日：2020-01-20
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: The present disclosure provides a gate driving unit and method, a gate driving module and circuit, and a display device. The gate driving unit includes: an external compensation control signal output terminal, a gate driving signal output terminal, an external compensation control signal output circuit, a gate driving signal output circuit, a pull-up control circuit and a pull-down node control circuit. The pull-up control circuit is configured to, under control of an enabling signal input by an enabling terminal and a current-stage driving signal, control a potential at a first node; under control of the potential at the first node, a first clock signal input by a first clock signal terminal, a second clock signal input by a second clock signal terminal and a potential at a pull-down node, control a potential at a pull-up control node; under control of the potential at the pull-up control node, control a potential at a pull-up node, thereby controlling the potential at the pull-up node to be an effective voltage in a preset time period of a blank time period.
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公开(公告)号：US20210201810A1
公开(公告)日：2021-07-01
申请号：US16966205
申请日：2020-01-20
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units (40) arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuitto receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.
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公开(公告)号：US20210201809A1
公开(公告)日：2021-07-01
申请号：US16965124
申请日：2020-01-19
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are provided. The shift register unit includes a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit. The first input circuit is configured to control a level of a first node, he output circuit is configured to provide an output signal at an output terminal, the first control circuit is configured to control a level of a second node under control of the level of the first node, the first reset circuit is configured to reset the first node and the output terminal under control of the level of the second node, and the storage circuit is electrically connected to the second node, and is configured to stabilize the level of the second node.
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公开(公告)号：US20210201805A1
公开(公告)日：2021-07-01
申请号：US16754200
申请日：2019-09-26
Inventor： Xuehuan FENG , Can YUAN , Yongqian LI
IPC: G09G3/3266 , G09G3/3275 , G09G3/3258
Abstract: An electronic panel, a display device and a driving method are disclosed. In the electronic panel, each row of subpixel units is divided into a plurality of subpixel unit groups, and each subpixel unit group includes a first subpixel unit and a second subpixel unit. The first subpixel unit includes a first light emitter unit, a first pixel driving circuit for driving the first light emitter unit to emit light, and a first sensing circuit for sensing the first pixel driving circuit; the second subpixel unit includes a second light emitter unit, a second pixel driving circuit for driving the second light emitter unit to emit light, and a second sensing circuit for sensing the second pixel driving circuit.
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