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公开(公告)号：US20250151583A1
公开(公告)日：2025-05-08
申请号：US19014454
申请日：2025-01-09
Inventor： Pan Xu , Zhidong Yuan , Yongqian Li , Can Yuan
IPC: H10K59/80 , H10K59/12 , H10K59/124
Abstract: Provided are a display panel and a method for manufacturing the same, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a separator located at the peripheral area and including at least one separation portion, each separation portion including a first and a second separation layer, and the orthographic projection of the first separation layer on the base substrate is within that of the second separation layer; a cathode including: a first cathode portion, and a second cathode spaced apart from the first cathode portion; and an encapsulation layer including a first and a second inorganic layer, and an organic layer located between the first and the second inorganic layer, wherein edges of the orthographic projections of the first inorganic layer, the organic layer, and the second inorganic layer on the base substrate overlap.
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公开(公告)号：US11955089B2
公开(公告)日：2024-04-09
申请号：US17680956
申请日：2022-02-25
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Pan Xu
IPC: G09G3/3275 , H10K59/131
CPC classification number: G09G3/3275 , H10K59/131 , G09G2310/061
Abstract: Provided is a display substrate. The display substrate includes two pixels arranged along a first direction and adjacent to each other on a base substrate, and a pixel circuit in each of the two pixels includes a drive transistor, a first reset transistor, and a second reset transistor. A display device is also provided.
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公开(公告)号：US11875750B2
公开(公告)日：2024-01-16
申请号：US17635471
申请日：2020-12-26
Inventor： Zhidong Yuan , Pan Xu , Can Yuan , Yongqian Li , Zhongyuan Wu
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/3233 , G11C19/287 , G09G2300/0819 , G09G2300/0852 , G09G2310/0286 , G09G2310/08
Abstract: An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.
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4.发明申请公开(公告)号：US20210408160A1
公开(公告)日：2021-12-30
申请号：US16963346
申请日：2019-09-27
Inventor： Can Yuan , Yongqian Li , Pan Xu , Zhidong Yuan , Meng Li , Xuehuan Feng , Zehua Ding
IPC: H01L27/32 , G09G3/3225
Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.
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公开(公告)号：US12232400B2
公开(公告)日：2025-02-18
申请号：US17640530
申请日：2021-04-29
Inventor： Pan Xu , Zhidong Yuan , Yongqian Li , Can Yuan
IPC: H10K59/80 , H10K59/12 , H10K59/124
Abstract: Provided are a display panel and a method for manufacturing the same, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a separator located at the peripheral area and including at least one separation portion, each separation portion including a first and a second separation layer, and the orthographic projection of the first separation layer on the base substrate is within that of the second separation layer; a cathode including: a first cathode portion, and a second cathode apart from the first cathode portion; and an encapsulation layer including a first and a second inorganic layer, and an organic layer located between the first and the second inorganic layer, wherein edges of the orthographic projections of the first inorganic layer, the organic layer, and the second inorganic layer on the base substrate overlap.
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Patent Agency Ranking
公开(公告)号：US12211449B2
公开(公告)日：2025-01-28
申请号：US17802580
申请日：2021-04-01
Inventor： Xuehuan Feng , Yongqian Li , Pan Xu
IPC: G09G3/3266
Abstract: A display panel has a display area and a fan-out region. The display panel includes: a substrate; a scan driving circuit including shift registers and clock signal lines, sub-pixels and signal transmission lines that are located in the display area; and a power supply voltage bus and connection lines that are located in the fan-out region. The sub-pixels are arranged in rows and columns, sub-pixels in a column are arranged along a second direction. A signal transmission line is electrically connected to column(s) of sub-pixels. The connection lines include first connection sub-lines, second connection sub-lines and third connection sub-lines that extend along the second direction and are located away from the sub-pixels. A first connection sub-line, a second connection sub-line and a third connection sub-line are electrically connected to the signal transmission line, the power supply voltage bus, and a clock signal line, respectively.
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公开(公告)号：US12148388B2
公开(公告)日：2024-11-19
申请号：US17921677
申请日：2021-11-08
Inventor： Zhidong Yuan , Yongqian Li , Pan Xu , Can Yuan
IPC: G09G3/3266 , G09G3/20 , G09G3/3233 , G11C19/28
Abstract: A light-emitting control shift register includes an input circuit, a pulse width adjustment circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The input circuit is configured to output a signal of a first signal input terminal. The pulse width adjustment circuit is configured to transmit the signal output from the input circuit to a pull-up node, and is further configured to output a signal of a second clock signal terminal to the pull-up node. The pull-up circuit is configured to output a voltage of a first voltage terminal to a signal output terminal. The pull-down control circuit is configured to output the voltage of the first voltage terminal, and is further configured to output a voltage of a second voltage terminal. The pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal.
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公开(公告)号：US11961466B2
公开(公告)日：2024-04-16
申请号：US17333483
申请日：2021-05-28
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Pan Xu
IPC: G11C19/28 , G06F3/041 , G09G3/3225 , G09G3/3266 , G09G3/3291 , G09G3/36 , H01L27/12
CPC classification number: G09G3/3225 , G11C19/28 , G09G2310/0286 , G09G2310/08
Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.
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公开(公告)号：US20240049569A1
公开(公告)日：2024-02-08
申请号：US17640530
申请日：2021-04-29
Inventor： Pan Xu , Zhidong Yuan , Yongqian Li , Can Yuan
IPC: H10K59/80 , H10K59/124 , H10K59/12
CPC classification number: H10K59/873 , H10K59/124 , H10K59/80523 , H10K59/1201
Abstract: Provided are a display panel and a method for manufacturing the same, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a separator located at the peripheral area and including at least one separation portion, each separation portion including a first and a second separation layer, and the orthographic projection of the first separation layer on the base substrate is within that of the second separation layer; a cathode including: a first cathode portion, and a second cathode apart from the first cathode portion; and an encapsulation layer including a first and a second inorganic layer, and an organic layer located between the first and the second inorganic layer, wherein edges of the orthographic projections of the first inorganic layer, the organic layer, and the second inorganic layer on the base substrate overlap.
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10.发明授权公开(公告)号：US11562673B2
公开(公告)日：2023-01-24
申请号：US17015475
申请日：2020-09-09
Inventor： Xuehuan Feng , Pan Xu
Abstract: The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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