公开(公告)号：US09811625B2

公开(公告)日：2017-11-07

申请号：US14697709

申请日：2015-04-28

Applicant: ARM LIMITED

Inventor： James Edward Myers

IPC: G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L27/0207 ,  H01L27/092

Abstract: A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row. Constraint data is specified identifying a subset of the standard cells that are allowed to be placed in each body biased row, and the layout is then generated by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row, and the constraint data for each body biased row. This enables a significant improvement in the benefits that can be achieved through the use of body biasing mechanisms, for example allowing a significant increase in switching speed of the circuit block to be achieved, without a significant increase in leakage current.

公开(公告)号：US20150355662A1

公开(公告)日：2015-12-10

申请号：US14731250

申请日：2015-06-04

Applicant: ARM Limited

Inventor： James Edward Myers ,  David Walter Flynn ,  David William Howard

IPC: G05F3/08 ,  G06F17/50

CPC classification number: G05F3/08 ,  G06F1/26 ,  G06F1/3287 ,  G06F17/5068 ,  H03K19/0016 ,  Y02D10/171

Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.

Abstract translation: 电子设备2具有电路4，其在被提供有第一电压电平VDD1和参考电压电平的第一电压域6中工作。 电压调节器14从高于第一电压电平VDD1的第二电压电平VDD2产生第一电压电平VDD1。 提供至少一个电源门20,30用于选择性地将电路4耦合到第一电压电平VDD1或参考电平之一。 用于功率门20,30的控制信号22在提供有从提供给电压调节器14的第二电压电平VDD2导出的较高电压电平VDD2或VDD3的第二电压域中产生。因此，现有的高压源 器件2可以重新用于将升压电压施加到电源门以提高电源门控的效率。