-
公开(公告)号：US09935634B2
公开(公告)日：2018-04-03
申请号：US14327004
申请日：2014-07-09
申请人： ARM Limited
IPC分类号： H03K19/01 , H03K19/0175
CPC分类号： H03K19/017509
摘要： An integrated circuit including a first voltage domain incorporates real time clock circuitry that communicates via communication circuitry with processing circuitry contained within a second voltage domain. The communication circuitry includes first parallel-to-serial conversion circuitry located within the first voltage domain, level shifting circuitry for passing serial signals between the voltage domains and second parallel-to-serial circuitry located in the second voltage domain.
-
公开(公告)号：US09720434B2
公开(公告)日：2017-08-01
申请号：US14731250
申请日：2015-06-04
申请人： ARM Limited
IPC分类号： H03K19/0175 , G05F3/08 , G06F17/50 , G06F1/32 , H03K19/00
CPC分类号： G05F3/08 , G06F1/26 , G06F1/3287 , G06F17/5068 , H03K19/0016 , Y02D10/171
摘要： An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.
-
公开(公告)号：US09170282B2
公开(公告)日：2015-10-27
申请号：US13895624
申请日：2013-05-16
申请人： ARM LIMITED
IPC分类号： H03K19/094 , G01R19/00 , H02M3/07
CPC分类号： H02M3/157 , G01R19/0084 , H02M3/07 , Y02B70/16
摘要： An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.
摘要翻译： 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。
-
公开(公告)号：US10885953B2
公开(公告)日：2021-01-05
申请号：US15764437
申请日：2016-11-30
申请人： ARM LIMITED
IPC分类号： G11C7/10 , G11C16/30 , G11C11/4093 , G11C11/419 , G11C5/14 , G11C11/4074
摘要： A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.
-
公开(公告)号：US10354721B2
公开(公告)日：2019-07-16
申请号：US15948918
申请日：2018-04-09
申请人： ARM Limited
发明人： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC分类号： G11C11/419 , G11C5/06 , G11C11/412
摘要： A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
-
公开(公告)号：US20180150120A1
公开(公告)日：2018-05-31
申请号：US15361405
申请日：2016-11-26
申请人： ARM Limited
发明人： Parameshwarappa Anand Kumar Savanth , Bal S. Sandhu , James Edward Myers , Alexander Stewart Weddell , David Walter Flynn
IPC分类号： G06F1/28 , G01R19/165
CPC分类号： G06F1/28 , G01R19/16576
摘要： Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.
-
公开(公告)号：US10007314B2
公开(公告)日：2018-06-26
申请号：US14907945
申请日：2014-06-16
申请人： ARM LIMITED
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F11/30 , G06F11/3024 , G06F11/3058 , G06F11/3096 , G06F13/00 , Y02D10/126 , Y02D10/172
摘要： Mechanisms are provided for energy management signalling with an apparatus for processing data, such as a system-on-chip integrated circuit (2). Processing circuitry (6, 8, 10) is coupled to consumer energy interface circuitry (14, 16, 18) which communicates with energy management circuitry (4). The energy management signals which are communicated include a static power consumption signal indicative of a level of power consumption which is independent of processing operations being performed and a dynamic power consumption signal indicative of a level of dynamic power consumption which is dependent upon the processing operations being performed.
-
公开(公告)号：US20170294222A1
公开(公告)日：2017-10-12
申请号：US15093457
申请日：2016-04-07
申请人： ARM Limited
发明人： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC分类号： G11C11/419 , G11C5/06
CPC分类号： G11C11/419 , G11C5/063 , G11C11/4125
摘要： A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
-
公开(公告)号：US09496785B2
公开(公告)日：2016-11-15
申请号：US14922783
申请日：2015-10-26
申请人： ARM Limited
CPC分类号： H02M3/157 , G01R19/0084 , H02M3/07 , Y02B70/16
摘要： An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.
-
公开(公告)号：US10664031B2
公开(公告)日：2020-05-26
申请号：US15361405
申请日：2016-11-26
申请人： ARM Limited
发明人： Parameshwarappa Anand Kumar Savanth , Bal S. Sandhu , James Edward Myers , Alexander Stewart Weddell , David Walter Flynn
IPC分类号： G06F1/00 , G06F1/28 , G01R19/165
摘要： Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.018 秒)
