公开(公告)号：US06320808B1

公开(公告)日：2001-11-20

申请号：US09686632

申请日：2000-10-11

申请人： Antonino Conte ,  Maurizio Gaibotti

发明人： Antonino Conte ,  Maurizio Gaibotti

IPC分类号： G11C700

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C2207/063

摘要： A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current. The differential comparator circuit compares the first and second voltages for providing a logic value relegates to a state of the memory cell to be read.

摘要翻译： 存储器读取放大器电路包括要被读取的至少一个存储器单元和与其连接的位线，连接到位线的第一预充电放大器电路。 第一级联电路连接在电源电压和存储单元之间，用于向存储单元提供第一电流。 存储器读取放大器电路还包括至少一个参考存储单元和连接到其上的参考位线，以及连接到参考位线的第二预充电放大器电路。 第二级联电路连接在电源电压和参考存储单元之间，用于向参考存储单元提供第二电流。 具有第一输入的差分比较器电路连接到第一共源共栅电路的控制端，用于基于第一电流接收第一电压，第二输入连接到第二共源共栅电路的控制端，用于接收第二电压 在第二个电流。 差分比较器电路比较第一和第二电压以提供降低要读取的存储器单元的状态的逻辑值。