公开(公告)号：US20160048334A1

公开(公告)日：2016-02-18

申请号：US14461865

申请日：2014-08-18

Applicant: Apple Inc.

Inventor： Robert E. Jeter

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/20 ,  G06F13/3625 ,  G06F2207/388 ,  G11C29/023 ,  G11C29/028

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

Abstract translation: 系统包括具有一个或多个存储阵列的存储器单元，以及可以耦合在存储器控制器和存储器单元之间的存储器接口单元。 存储器接口单元可以包括可以生成用于控制对存储器单元的读取和写入访问的定时信号的定时单元，以及可以以预定间隔校准定时单元的控制单元。 然而，响应于给定的预定间隔的发生，存储器接口单元可以被配置为使用多个部分校准段校准定时单元。