公开(公告)号：US11013116B2

公开(公告)日：2021-05-18

申请号：US16621521

申请日：2019-03-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liqiang Chen ,  Paoming Tsai ,  Weifeng Zhou ,  Chen Xu ,  Jifeng Tan

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/30 ,  H05K3/36 ,  H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  G06F3/033 ,  G06F3/038 ,  G06F3/041 ,  G06F3/044

Abstract: A flexible assembly for a display device and the display device are provided. The flexible assembly includes a flexible substrate, and a first output pad, a second output pad, a third output pad and a fourth output pad that are arranged on the substrate. The first output pad, the second output pad, the third output pad and the fourth output pad are sequentially arranged along a first direction and are spaced apart from each other. A pitch is between each output pad and an adjacent output pad, and the pitch is a sum of a spacing distance between each output pad and the adjacent output pad and a width of the adjacent output pad in the first direction. The pitch between the first output pad and the adjacent second output pad is smaller than the pitch between the third output pad and the adjacent fourth output pad.

公开(公告)号：US10998189B2

公开(公告)日：2021-05-04

申请号：US16569311

申请日：2019-09-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng Guan ,  Zhi Wang ,  Chen Xu

IPC: H01L21/02 ,  B23K26/06 ,  H01L21/306 ,  H01L23/544 ,  H01L27/12 ,  B23K26/354

Abstract: A laser annealing process of a drive backplane includes: providing a mask, which has a light transmission area; and sequentially moving the mask to cover different areas of an amorphous silicon layer of the drive backplane, and annealing the amorphous silicon layer exposed in the light transmission area to form a poly-silicon pattern.

公开(公告)号：US10997936B2

公开(公告)日：2021-05-04

申请号：US16475473

申请日：2019-01-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chen Xu ,  Xueguang Hao ,  Yong Qiao ,  Xinyin Wu

IPC: G09G3/36 ,  G11C19/28

Abstract: A shift register unit, a gate drive circuit and a display device are disclosed. The shift register unit includes an input circuit, an output circuit, a reset circuit, a control circuit and a reset stabilizing circuit. The input circuit is configured to write an input signal into a first node in response to an input start signal. The output circuit is configured to output a preparatory output signal to an output terminal under control of an electric level of the first node. The reset circuit is configured to reset the output terminal under control of an electric level of a second node. The control circuit is configured to apply a first voltage signal to the second node in response to a control signal. The reset stabilizing circuit is configured to apply a second voltage signal to the first node in response to a reset stabilizing signal.

公开(公告)号：US20170194407A1

公开(公告)日：2017-07-06

申请号：US15302934

申请日：2016-04-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guang Li ,  Chen Xu

IPC: H01L27/32 ,  G09G3/3208

CPC classification number: H01L27/3262 ,  G09G3/3208 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/061 ,  H01L21/77 ,  H01L27/124 ,  H01L27/3276 ,  H01L2227/323

Abstract: The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.

公开(公告)号：US09698208B1

公开(公告)日：2017-07-04

申请号：US15302934

申请日：2016-04-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guang Li ,  Chen Xu

IPC: H01L27/14 ,  H01L27/32 ,  G09G3/3208 ,  H01L27/12

CPC classification number: H01L27/3262 ,  G09G3/3208 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/061 ,  H01L21/77 ,  H01L27/124 ,  H01L27/3276 ,  H01L2227/323

Abstract: The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.