Abstract:
A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.
Abstract:
A process for receiving a composite signal transmitted via a nonlinear data transmission channel comprising a first signal UL and a second signal LL. The process comprises the following: demodulating and decoding said first signal UL by means of a first demodulation and decoding chain in order to regenerate said first information UL; recoding and shaping to produce a continuous time waveform; applying a nonlinearity function based on a set of coefficients updated according to an adaptive correlation calculation process to said continuous time waveform; subtracting the result of said nonlinearity function from said composite signal in order to generate a result E; and demodulating and decoding said result E by means of a second demodulation and decoding chain in order to regenerate said second information LL.
Abstract:
A linear interpolation operator for determining the value y of a function of x when one knows the value y1 corresponding to x1, and a value y2 corresponding to x2 (where x2
Abstract:
The present invention relates to a digital filter for a phase-locked loop receiving at least one input signal having a predetermined period, including an element of accumulation of frequency values receiving the output of a phase detector; and an element of accumulation of phase values receiving a weighted sum of the output of the phase detector and of the content of the element of accumulation of frequency values. Each of the accumulation elements includes several frequency or phase value storage locations, circuitry being provided for successively making operative the storage locations in the phase-locked loop during a period of the input signal.
Abstract:
A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line. In another preferred embodiment, the repeater also includes a conditional circuit that is controlled by an electronic circuits connected to the first section. The conditional circuit selectively enables or prevents transmission between the first and second sections of the line.
Abstract:
A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference area, when the demodulator is wrongly adjusted.
Abstract:
In a Reed-Solomon error correction system, the coefficients of the syndrome polynomial of degree 2t-1 are stored in a first set of registers R, coefficients 0,0 . . . ,0,1,0 are stored in a second set of registers .lambda., and a first number is stored in a counter. Coefficients 1,0 . . . ,0 are stored in a third set of registers Q, zeroes are stored in a fourth set of registers .mu., and a number exceeding the first number by 1 is stored in an indicator register. a) If the content of the counter is higher than or equal to the content of the indicator register, or if the content of the last register of the first set of registers R is zero, value Q.sub.2t-1 R.sub.i-1 +R.sub.2t-1 Q.sub.i-1 is stored in each register R.sub.i of the first set of registers R, and value Q.sub.2t-1 .lambda..sub.i-1 +R.sub.2t-1 .lambda..sub.i-1 is stored in each register .lambda..sub.i of the third set of registers .lambda.. b) Otherwise, the contents of the first set of registers R, the second set of registers .lambda., and the counter are further transferred into the third set of registers Q, the fourth set of registers .mu., and the indicator register, respectively. Steps a) or b) are repeated until the content of the counter is decremented by t.
Abstract:
Compositions containing Bifenox and Linuron in combination with a mineral oil, such as white oil, show a remarkable synergism of the constituents and are of use as pre-harvest defoliants for crop plants, e.g. for desiccation of potato plants.
Abstract:
A method of preparing varnishes based on polyester resin, which do not turn green on polymerization. It comprises forming a reducing agent during polycondensation, by reacting a magnesium compound with the reagents present. Applicable chiefly to the furniture industry.