公开(公告)号：US20140217588A1

公开(公告)日：2014-08-07

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

公开(公告)号：US20140213037A1

公开(公告)日：2014-07-31

申请号：US13755246

申请日：2013-01-31

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Nicholas LiCausi ,  Jody Fronheiser ,  Errol Todd Ryan

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3105 ,  H01L29/66795

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的方法。 根据一个实施例，该方法包括形成至少部分地由限制隔离材料界定的半导体衬底的一部分。 形成衬垫电介质覆盖在限制隔离材料上，并被处理以钝化其表面。然后，半导体材料的外延层生长在半导体衬底的该部分上。