公开(公告)号：US20190244911A1

公开(公告)日：2019-08-08

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L23/544 ,  H01L21/68 ,  G01B11/27 ,  G01N21/552

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US10199270B2

公开(公告)日：2019-02-05

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

公开(公告)号：US20180342421A1

公开(公告)日：2018-11-29

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

公开(公告)号：US20160190207A1

公开(公告)日：2016-06-30

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

Abstract translation: 提供了包括用于磁阻随机存取存储器（MRAM）的磁性隧道结（MTJ）和用于制造这种集成电路的方法的集成电路。 在一个示例中，制造集成电路的方法包括在金属互连上形成下电极。 金属互连设置在半导体衬底之上并且与基本上垂直于半导体衬底的法线对准。 下电极包括导电金属插头。 在与正常轴对准的下电极上形成MTJ堆叠。

公开(公告)号：US08907483B2

公开(公告)日：2014-12-09

申请号：US13648433

申请日：2012-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Abstract translation: 提供了一种用于形成半导体器件的方法。 通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。 然后通过超低k层和盖层形成通孔。 一旦形成通孔，就可以选择性地将阻挡层（例如钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或其它能够用作铜（CU）扩散阻挡层的金属） 通孔的底面。 然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。 然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

公开(公告)号：US08859419B2

公开(公告)日：2014-10-14

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/58 ,  H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0352 ,  H01L23/22 ,  H01L23/24 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US09576852B2

公开(公告)日：2017-02-21

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。

公开(公告)号：US20160118292A1

公开(公告)日：2016-04-28

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US09318436B2

公开(公告)日：2016-04-19

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US09165770B2

公开(公告)日：2015-10-20

申请号：US14037774

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。