公开(公告)号：US20240363763A1

公开(公告)日：2024-10-31

申请号：US18771108

申请日：2024-07-12

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/823412 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869

摘要： A device comprises a vertical transistor and a shielding material comprising a conductive material having a P+ type conductivity. The vertical transistor includes an electrode, a dielectric material adjacent to the electrode, and a channel region adjacent to the dielectric material. The channel region comprises a composite structure including at least two semiconductor materials. Also disclosed is a device comprising a first electrically conductive line, vertical transistors overlying the first conductive line, a second electrically conductive line overlying the vertical transistors, and a shielding material positioned between the two adjacent vertical transistors. Each of the vertical transistors comprises a gate electrode, a gate dielectric material on opposite sides of the gate electrode, and a channel region comprising a composite structure including at least two oxide semiconductor materials. The gate dielectric material positions between the gate electrode and the channel region. The shielding material comprises an electrically conductive material.

公开(公告)号：US12131905B2

公开(公告)日：2024-10-29

申请号：US16923478

申请日：2020-07-08

申请人： Samsung Electronics Co., Ltd.

发明人： Keunwook Shin ,  Kyungeun Byun ,  Hyeonjin Shin ,  Soyoung Lee ,  Changseok Lee

IPC分类号： H01L21/02 ,  C23C16/26 ,  C23C16/50 ,  H01L29/16

CPC分类号： H01L21/02527 ,  C23C16/26 ,  C23C16/50 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/0262 ,  H01L29/1606

摘要： A graphene structure and a method of forming the graphene structure are provided. The graphene structure includes directly grown graphene that is directly grown on a surface of a substrate and has controlled surface energy.

公开(公告)号：US20240347612A1

公开(公告)日：2024-10-17

申请号：US18751382

申请日：2024-06-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SZU-YU WANG ,  CHIA-WEI HU

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/42328 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/40114 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66545

摘要： A semiconductor structure for a memory device is provided. The semiconductor structure includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer. The first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration. The second gate structure includes a p-type gate structure, and second dopant concentration of the second layer is greater than the first dopant concentration of the first layer.

公开(公告)号：US12112947B2

公开(公告)日：2024-10-08

申请号：US17655247

申请日：2022-03-17

申请人： Tokyo Electron Limited

发明人： Tatsuya Miyahara ,  Daisuke Suzuki ,  Yoshihiro Takezawa ,  Yuki Tanabe

IPC分类号： H01L21/02 ,  C23C16/02 ,  C23C16/24 ,  C23C16/52 ,  C23C16/56

CPC分类号： H01L21/02667 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02645

摘要： A method of crystallizing an amorphous silicon film includes depositing the amorphous silicon film on a seed layer formed over a substrate while heating the amorphous silicon film at a first temperature, and forming a crystal nucleus in an outer layer of the amorphous silicon film by causing migration of silicon in the outer layer by heating the amorphous silicon film at a second temperature higher than the first temperature.

公开(公告)号：US20240321578A1

公开(公告)日：2024-09-26

申请号：US18680924

申请日：2024-05-31

申请人： Fudan University

发明人： Liwei LIU ,  Zhenggang CAI ,  Siwei XUE ,  Peng ZHOU

IPC分类号： H01L21/02 ,  H01L29/786

CPC分类号： H01L21/02568 ,  H01L21/02499 ,  H01L21/0262 ,  H01L29/78681

摘要： A method for preparing a wafer-scale two-dimensional (2D) material array includes the following steps. Water and alcohol solvent are mixed to obtain a mixed solution. A polydimethylsiloxane (PDMS) stamp with micro posts is prepared. A monolayer two-dimensional transition metal dichalcogenides (2D-TMDs) film is continuously grown on a growth substrate. The PDMS stamp is put upside down to allow the micro posts to adhere to the monolayer 2D-TMDs film, so as to obtain a PDMS stamp-2D-TMDs film-growth substrate combination. The PDMS stamp-2D-TMDs film-growth substrate combination is immersed in the mixed solution to separate the monolayer 2D-TMDs film from the growth substrate. A portion of the monolayer 2D-TMDs film which is not in contact with upper surfaces of the micro posts is removed to obtain a patterned 2D-TMDs film. The patterned 2D-TMDs film is transferred to a target substrate to obtain the wafer-scale 2D material array.

公开(公告)号：US20240313056A1

公开(公告)日：2024-09-19

申请号：US18577827

申请日：2022-07-04

申请人： Paragraf Limited

发明人： Sebastian DIXON ,  Jaspreet KAINTH ,  Ivor GUINEY ,  Thomas James BADCOCK

IPC分类号： H01L29/16 ,  H01L21/02

CPC分类号： H01L29/1606 ,  H01L21/02376 ,  H01L21/02458 ,  H01L21/02483 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/0262

摘要： There is provided a graphene substrate comprising: a graphene layer structure directly on a metal oxide layer, said metal oxide layer directly on a support layer; wherein the metal oxide layer has a thickness of less than 5 nm and is selected from the group consisting of Al2O3, HfO2, MgO, MgAl2O4, Ta2O5, Y2O3, ZrO2 and YSZ; and wherein the support layer is BN, AlN, GaN, SiC, diamond, or a combination thereof.

公开(公告)号：US12074224B2

公开(公告)日：2024-08-27

申请号：US17591690

申请日：2022-02-03

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC分类号： H01L29/786 ,  C23C16/40 ,  C23C16/455 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/67 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262

摘要： A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

公开(公告)号：US20240282813A1

公开(公告)日：2024-08-22

申请号：US18171119

申请日：2023-02-17

申请人： Applied Materials, Inc.

发明人： Amirhasan Nourbakhsh ,  Raman Gaire ,  Roger Quon ,  Siddarth Krishnan

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/66712 ,  H01L29/7802

摘要： A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

公开(公告)号：US20240274671A1

公开(公告)日：2024-08-15

申请号：US18646141

申请日：2024-04-25

申请人： Resonac Corporation

发明人： Naoto ISHIBASHI ,  Keisuke FUKADA

IPC分类号： H01L29/36 ,  C30B25/14 ,  C30B25/16 ,  C30B29/36 ,  H01L21/02 ,  H01L29/16

CPC分类号： H01L29/365 ,  C30B25/14 ,  C30B25/165 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02584 ,  H01L21/0262 ,  H01L29/1608

摘要： A SiC epitaxial wafer of the present invention includes a SiC single crystal substrate, and a high concentration layer that is provided on the SiC single crystal substrate and has an average value of an n-type doping concentration of 1×1018/cm3 or more and 1×1019/cm3 or less, and in-plane uniformity of the doping concentration of 30% or less.

公开(公告)号：US20240274463A1

公开(公告)日：2024-08-15

申请号：US18108407

申请日：2023-02-10

申请人： Applied Materials, Inc.

发明人： Zhepeng CONG ,  Nimrod SMITH ,  Tao SHENG ,  Chen-Ying WU ,  Hui CHEN ,  Xinning LUAN

IPC分类号： H01L21/687 ,  H01L21/02

CPC分类号： H01L21/68735 ,  H01L21/0262

摘要： The present disclosure relates to overlapping substrate supports and pre-heat rings, and related process kits, processing chambers, methods, and components to facilitate process adjustability. In one or more embodiments, a substrate support applicable for use in semiconductor manufacturing includes a first side face and a second side face opposing the first side face. The first side face includes a support surface. The second side face includes a backside surface, and a first shoulder protruding relative to the backside surface. The first shoulder is disposed outwardly of the backside surface. The substrate support includes an arcuate outer face extending between the first side face and the second side face.