公开(公告)号：US07423313B2

公开(公告)日：2008-09-09

申请号：US11655060

申请日：2007-01-19

申请人： Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。

公开(公告)号：US20080135958A1

公开(公告)日：2008-06-12

申请号：US11943112

申请日：2007-11-20

申请人： Takeshi KAJIYAMA ,  Yoshiaki Asao ,  Akihiro Nitayama

发明人： Takeshi KAJIYAMA ,  Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/228

摘要： A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.

摘要翻译： 磁性随机存取存储器包括磁阻效应元件，其具有设置在固定层和记录层之间的固定层，记录层和非磁性层，并且固定层和记录层的磁化方向被带入 根据在固定层和记录层之间流动的电流的方向，形成平行状态或反平行状态;第一触点连接到记录层，并且记录层和记录层之间的接触区域 第一触点小于记录层的面积，盖层设置在第一触点和记录层之间，并直接与第一触点接触并且具有高于记录层电阻的电阻 。

公开(公告)号：US20080080233A1

公开(公告)日：2008-04-03

申请号：US11839265

申请日：2007-08-15

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： G11C11/00 ,  H01L21/00

CPC分类号： H01L27/228 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

摘要翻译： 磁性随机存取存储器包括第一布线，形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件，以及 具有形成在固定层和记录层之间的固定层，记录层和非磁性层，形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层，形成第一侧绝缘膜 在金属层的侧表面，磁阻效应元件和第一布线，与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。

公开(公告)号：US20070187745A1

公开(公告)日：2007-08-16

申请号：US11655060

申请日：2007-01-19

申请人： Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。

公开(公告)号：US5358808A

公开(公告)日：1994-10-25

申请号：US94442

申请日：1993-07-21

申请人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hishimoto ,  Hirotsugu Wada

发明人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hishimoto ,  Hirotsugu Wada

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F1/29

摘要： An exposure mask for lithography, a method of manufacturing the same, and an exposure method using the same are disclosed. A light-transmitting opening of the exposure mask has a main light-transmitting region located in the middle of the opening and having a first optical path length, and phase shift regions adjacent to a light-shielding layer and having a second optical path length, different from the first optical path length. Light transmitted through each phase shift region interferes with light transmitted through the main light-transmitting region at the edges of the light-transmitting opening, thus enabling a sharp photo-intensity distribution of total transmitted light to be obtained. As a result, the resolution of the exposure mask is improved.

摘要翻译： 公开了一种用于光刻的曝光掩模，其制造方法和使用其的曝光方法。 曝光掩模的透光开口具有位于开口中间并具有第一光程长度的主透光区域和与遮光层相邻并且具有第二光程长度的相移区域， 不同于第一光路长度。 透过各相移区域的光干涉透过透光开口边缘的主透光区域的光，从而能够得到总透光的尖锐的光强度分布。 结果，改善了曝光掩模的分辨率。

公开(公告)号：US5311050A

公开(公告)日：1994-05-10

申请号：US796602

申请日：1991-11-22

申请人： Akihiro Nitayama ,  Koji Sakui

发明人： Akihiro Nitayama ,  Koji Sakui

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L29/4236

摘要： A semiconductor device including a semiconductor substrate 1 and at least one first column-shaped semiconductor layer 10 of a first channel type formed on semiconductor substrate 1 in order of first, second and third regions, and having a side surface. At least one second column-shaped semiconductor layer 11 of a second channel type is selectively laminated on first semiconductor layer 10 in order of first, second and third regions, and having a side surface. A gate insulation film 8 is formed on the side surfaces of first semiconductor layer 10 and second semiconductor layer 11. A gate electrode 9 is formed on the insulation film 8 extending to an external portion of first semiconductor layer 10. A first source layer 2 and first drain layer 4 are respectively formed in the first and third regions of first semiconductor layer 10. A second source layer 7 and second drain layer 5 are respectively formed in the first and third regions of semiconductor layer 11. An input terminal 14 is connected to gate electrode 9 to lead out to the exterior of first semiconductor layer 10. An output terminal 15 is connected to second drain layer 5 formed on and in low-resistance contact with first drain layer. A first power source terminal 16 is connected to first source layer 2 of first semiconductor layer 10, and a second power source terminal 17 is connected to second source layer 7.

摘要翻译： 一种半导体器件，包括半导体衬底1和形成在半导体衬底1上的第一沟道型的至少一个第一柱状半导体层10，其具有第一，第二和第三区域的顺序并且具有侧表面。 第二沟道型的至少一个第二列状半导体层11按照第一，第二和第三区域的顺序选择性层压在第一半导体层10上，并具有侧面。 在第一半导体层10和第二半导体层11的侧表面上形成栅极绝缘膜8.在延伸到第一半导体层10的外部的绝缘膜8上形成栅电极9.第一源极层2和 第一漏极层4分别形成在第一半导体层10的第一和第三区域中。第二源极层7和第二漏极层5分别形成在半导体层11的第一和第三区域中。输入端子14连接到 栅极电极9引出到第一半导体层10的外部。输出端子15连接到形成在第一漏极层上并与第一漏极层低电阻接触的第二漏极层5。 第一电源端子16连接到第一半导体层10的第一源极层2，第二电源端子17连接到第二源极层7。