公开(公告)号：US20240355393A1

公开(公告)日：2024-10-24

申请号：US18760318

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  G11C11/16 ,  H10B12/00 ,  H10B41/30

CPC classification number: G11C16/08 ,  G11C11/1657 ,  H10B12/053 ,  H10B41/30

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US20240339144A1

公开(公告)日：2024-10-10

申请号：US18364674

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Ching-Huang Wang ,  Hung Cho Wang ,  Tien-Wei Chiang ,  Wen-Chun You

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657

Abstract: An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.

公开(公告)号：US12051455B2

公开(公告)日：2024-07-30

申请号：US17845274

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jae Lee ,  Jihun Byun

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.

公开(公告)号：US20240237551A1

公开(公告)日：2024-07-11

申请号：US18615459

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US20240224812A1

公开(公告)日：2024-07-04

申请号：US18148392

申请日：2022-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Michael Rizzolo ,  Julien Frougier

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a magneto-resistive random access memory (MRAM) formed at a backside of a wafer. A self-aligning micro stud and silicide layer can directly electrically connect the MRAM to a source/drain (S/D) of a transistor in the MRAM region of the semiconductor device.

公开(公告)号：US12020737B2

公开(公告)日：2024-06-25

申请号：US17464808

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Hisanori Aikawa

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/10 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85

Abstract: A memory device includes a memory cell array, first and second memory cells, first and second read circuits, and first and second write circuits. The memory cell array includes first and second sub-arrays. The first memory cells are included in each of the first sub-arrays. The second memory cells are included in each of the second sub-arrays. The first and second read circuits are provided for reading data of the first and second memory cells, respectively. The first and second write circuits are provided for writing data to the first and second memory cells, respectively. An area of the first sub-array is different from an area of the second sub-array.

公开(公告)号：US11963456B2

公开(公告)日：2024-04-16

申请号：US17658838

申请日：2022-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dimitri Houssameddine ,  Kangguo Cheng ,  Julien Frougier ,  Ruilong Xie

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/01 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  H10B61/22

Abstract: Embodiments of present invention provide a method of improving yield of making MRAM arrays. More specifically, the method includes receiving an MRAM array; identifying a weak MRAM cell from the MRAM array wherein the weak MRAM cell includes an access transistor; and modifying the access transistor. In one embodiment, modifying the access transistor includes performing a hot carrier injection into a gate dielectric layer of the access transistor.

公开(公告)号：US20240079040A1

公开(公告)日：2024-03-07

申请号：US18225908

申请日：2023-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/16

CPC classification number: G11C11/1655 ,  G11C11/161 ,  G11C11/1657

Abstract: A memory device including a three-dimensional racetrack and an operating method of the memory device are provided. The memory device includes a first racetrack, a first transistor, a first domain index controller, a bit line driver, a plurality of first magnetic tunnel junction (MTJ) elements, a plurality of first cell transistors, and a source line driver.

公开(公告)号：US20240005976A1

公开(公告)日：2024-01-04

申请号：US17885980

申请日：2022-08-11

Applicant: Deliang Fan ,  Shaahin Angizi

Inventor： Deliang Fan ,  Shaahin Angizi

IPC: G11C11/16 ,  H03K19/20

CPC classification number: G11C11/1673 ,  H03K19/20 ,  G11C11/1657 ,  G11C11/161 ,  G11C11/1675

Abstract: A Processing-in-Memory (PIM) design is disclosed that converts any memory sub-array based on non-volatile resistive bit-cells into a potential processing unit. The memory includes the data matrix stored in terms of resistive states of memory cells. Through modifying peripheral circuits, the address decoder receives three addresses and activates three memory rows with resistive bit-cells (i.e., data operands). In this way, three bit-cells are activated in each memory bit-line and sensed simultaneously, leading to different parallel resistive levels at the sense amplifier side. By selecting different reference resistance levels and a modified sense amplifier, a full-set of single-cycle 1-/2-3-input reconfigurable complete Boolean logic and full-adder outputs could be intrinsically readout based on input operand data in the memory array.

公开(公告)号：US20230380185A1

公开(公告)日：2023-11-23

申请号：US18366702

申请日：2023-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HUNG-CHANG YU

IPC: H10B61/00 ,  H01L27/10 ,  G11C11/16 ,  G11C11/15 ,  H10B63/00

CPC classification number: H10B61/20 ,  H01L27/101 ,  G11C11/1655 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/15 ,  H10B63/32

Abstract: A method includes: providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit; determined an operation mode of a memory array; providing a first current corresponding to a positive temperature coefficient by the driving circuit in response to the operation mode being a read operation on the memory array; and providing a second current corresponding to a negative temperature coefficient by the driving circuit in response to the operation mode being a write operation on the memory array.