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公开(公告)号：US07692963B2
公开(公告)日：2010-04-06
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译： 本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流 的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。
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公开(公告)号：US20080305588A1
公开(公告)日：2008-12-11
申请号：US12222143
申请日：2008-08-04
申请人： Takeshi Hamamoto , Akihiro Nitayama
发明人： Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.
摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。
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公开(公告)号：US07759255B2
公开(公告)日：2010-07-20
申请号：US11561700
申请日：2006-11-20
申请人： Takeshi Hamamoto , Akihiro Nitayama
发明人： Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8239
CPC分类号： H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10894 , H01L27/10897 , H01L27/1203 , H01L29/7841
摘要： In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.
摘要翻译： 在本发明的一个实施例中，一种制造半导体器件的方法包括：在半导体衬底上形成被去除层; 在被去除层上形成半导体层; 在SOI区域中形成穿过所述半导体层到所述被去除层的沟槽; 通过使用沟槽去除待去除的层并产生空腔; 以及在所述空腔中形成绝缘膜。
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公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。
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公开(公告)号：US07977738B2
公开(公告)日：2011-07-12
申请号：US12497010
申请日：2009-07-02
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。
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公开(公告)号：US5106774A
公开(公告)日：1992-04-21
申请号：US650992
申请日：1991-02-04
申请人： Katsuhiko Hieda , Fumio Horiguchi , Takeshi Hamamoto , Akihiro Nitayama , Kazumasa Sunouchi , Kei Kurosawa , Fujio Masuoka
发明人： Katsuhiko Hieda , Fumio Horiguchi , Takeshi Hamamoto , Akihiro Nitayama , Kazumasa Sunouchi , Kei Kurosawa , Fujio Masuoka
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.
摘要翻译： 公开了一种动态随机存取存储器，其包括具有形成在半导体衬底中的晶体管的沟槽型存储单元和布置在形成在衬底中并具有沟槽结构的沟槽中的电容器。 电容器包括形成在衬底上的杂质掺杂半导体层，以围绕沟槽并且具有与衬底的导电类型相反的导电类型，形成在沟槽中的第一电容器电极和具有绝缘层叠的部分的第二电容器电极 所述第一电容器电极在沟槽中。
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公开(公告)号：US20100019304A1
公开(公告)日：2010-01-28
申请号：US12497010
申请日：2009-07-02
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译： 半导体存储器件包括电漂浮体; 来源 下水道 栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括与排水管相同导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。
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公开(公告)号：US20080237695A1
公开(公告)日：2008-10-02
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。
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公开(公告)号：US07732271B2
公开(公告)日：2010-06-08
申请号：US12222143
申请日：2008-08-04
申请人： Takeshi Hamamoto , Akihiro Nitayama
发明人： Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.
摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。
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公开(公告)号：US20080239789A1
公开(公告)日：2008-10-02
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/24 , H01L27/108 , G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译： 本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流 的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。
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