公开(公告)号：US09634139B1

公开(公告)日：2017-04-25

申请号：US15345707

申请日：2016-11-08

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7836

Abstract: A dual-well metal oxide semiconductor (MOS) device includes: a semiconductor substrate, an active layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, a second conductive type connection region, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and a PN junction is formed therebetween right below the gate. The second conductive type connection region is formed right below a spacer of the gate, and is connected to the second conductive type source in a lateral direction to avoid OFF-channel. The second conductive type connection region is formed by a tilt-angle ion implantation process step through the spacer.

公开(公告)号：US09525028B1

公开(公告)日：2016-12-20

申请号：US15066207

申请日：2016-03-10

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/823493 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A dual-well metal oxide semiconductor (MOS) device includes: a substrate, an epitaxial layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a first conductive type lightly doped diffusion (LDD) region, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and an PN junction is formed between the second conductive type well and the first conductive type well. The MOS device includes LDD regions of opposite conductive types, each located in a corresponding well of a corresponding conductive type, to reduce the channel length.

Abstract translation: 双阱金属氧化物半导体（MOS）器件包括：衬底，外延层，第一导电类型阱，第一导电类型体区域，第二导电类型阱，栅极，第一导电类型轻掺杂扩散（ LDD）区域，第二导电类型轻掺杂扩散（LDD）区域，第二导电型源极和第二导电类型漏极。 第二导电型阱在横向方向上连接到第一导电类型阱，并且在第二导电类型阱和第一导电类型阱之间形成PN结。 MOS器件包括具有相对导电类型的LDD区域，每个LDD区域位于相应导电类型的相应阱中，以减小沟道长度。

公开(公告)号：US09520470B1

公开(公告)日：2016-12-13

申请号：US14939913

申请日：2015-11-12

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.

Abstract translation: 横向双扩散金属氧化物半导体器件包括：P型衬底，外延层，P型高压阱，P型体区，N型阱，隔离氧化物区域，漂移氧化物 区域，栅极，N型接触区域，P型接触区域，顶部源极，底部源极和N型漏极。 P型体区在P型高电压阱和外延层的表面之间并连接。 P型体区域包括在外延层的表面下方并间接接触的峰值浓度区域，其中峰值浓度区域在P型体区域中具有最高的P型杂质浓度。 P型体区域的P型杂质浓度高于预定阈值，以抑制寄生双极晶体管不导通。