公开(公告)号：US07534689B2

公开(公告)日：2009-05-19

申请号：US11562209

申请日：2006-11-21

Applicant: Rohit Pal ,  Igor Peidous ,  David Brown

Inventor： Rohit Pal ,  Igor Peidous ,  David Brown

IPC: H01L21/20

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。

公开(公告)号：US20080237811A1

公开(公告)日：2008-10-02

申请号：US11694057

申请日：2007-03-30

Applicant: Rohit Pal ,  David F. Brown

Inventor： Rohit Pal ,  David F. Brown

IPC: H01L23/544

CPC classification number: H01L22/20

Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.

Abstract translation: 用于捕获工艺历史的方法包括至少执行用于在半导体衬底上形成特征的第一工艺。 在执行第一处理之后，在半导体基板的第一区域上形成第一盖。 执行至少第二过程，用于在除了第一区域之外的第二区域中形成特征，同时将第一盖留在适当位置，从而防止第一盖子覆盖的第一区域中的特征暴露于第二过程。 在第一区域中测量第一特征的第一特征，并且测量第二区域中的第二特征的第二特征。 晶片包括设置在第一区域中的第一部分完成特征。 在第一部分完成的特征之上形成第一盖。 第二部分完成的特征被布置在不同于第一区域的晶片的第二区域中。 第二部分完成的功能处于完成的后期，而不是第一部分完成的功能。

公开(公告)号：US20080142835A1

公开(公告)日：2008-06-19

申请号：US11611784

申请日：2006-12-15

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。 应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。