公开(公告)号：US10983381B2

公开(公告)日：2021-04-20

申请号：US16534430

申请日：2019-08-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Ki Jeong ,  Hyun Joon Kim ,  Kyung Bae Kim ,  Kyung Hoon Chung ,  Chong Chul Chai

IPC: G02F1/1333 ,  F21V8/00 ,  G09G3/20

Abstract: A tiled display device includes an array of a plurality of display panels. Each of the plurality of display panels includes a plurality of pixels constituting a plurality of pixel rows and a plurality of pixel columns, a data distributor disposed between a first pixel of a first pixel row among the plurality of pixel rows and a second pixel of the first pixel row adjacent to the first pixel in a first direction, and a scan driver disposed between the second pixel and a third pixel adjacent to the second pixel in the first direction.

公开(公告)号：US10120254B2

公开(公告)日：2018-11-06

申请号：US14934931

申请日：2015-11-06

Applicant: Samsung Display Co., Ltd.

Inventor： Hoon Kim ,  Hyun Joon Kim ,  Ki Chul Shin

IPC: G02F1/1362 ,  G02F1/1343

Abstract: A liquid crystal display includes a first substrate and a second substrate facing each other. The liquid crystal display further includes a gate line and a data line disposed on the first substrate, a first thin film transistor and a second thin film transistor connected to the gate line and the data line, a first subpixel electrode connected to the first thin film transistor, a third thin film transistor connected to the second thin film transistor, a second subpixel electrode connected to the third thin film transistor; and a liquid crystal layer interposed between the first substrate and the second substrate. The third thin film transistor includes a first terminal applied with a same constant voltage during all times of operation, a second terminal directly connected to the second thin film transistor, and a third terminal connected to the second subpixel electrode.

公开(公告)号：US09673806B2

公开(公告)日：2017-06-06

申请号：US14334104

申请日：2014-07-17

Applicant: Samsung Display Co. Ltd.

Inventor： Jong Hee Kim ,  Hyun Joon Kim ,  Cheol Gon Lee ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G5/00 ,  H03K17/16 ,  H03K17/687 ,  H03K17/00 ,  G09G3/3266

CPC classification number: H03K17/162 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2320/045 ,  H03K17/002 ,  H03K17/6871

Abstract: A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.