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    Virtually-Tagged Instruction Cache with Physically-Tagged Behavior
    62.
    发明申请
    Virtually-Tagged Instruction Cache with Physically-Tagged Behavior 有权
    具有物理标记行为的几何标记指令缓存

    公开(公告)号：US20070250666A1

    公开(公告)日：2007-10-25

    申请号：US11468850

    申请日：2006-08-31

    申请人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

    发明人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

    摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

    摘要翻译： 一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。 指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

    Debug circuit comparing processor instruction set operating mode
    63.
    发明授权
    Debug circuit comparing processor instruction set operating mode 有权
    调试电路比较处理器指令集的工作模式

    公开(公告)号：US08352713B2

    公开(公告)日：2013-01-08

    申请号：US11463379

    申请日：2006-08-09

    申请人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    发明人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    IPC分类号： G06F9/48

    CPC分类号： G06F11/3648

    摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

    摘要翻译： 处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。 当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。 警报或指示还可以依赖于在预定目标地址范围内的指令地址。 警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。 可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。 附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

    Sliding-window, block-based branch target address cache
    65.
    发明授权
    Sliding-window, block-based branch target address cache 有权
    滑动窗口，基于块的分支目标地址缓存

    公开(公告)号：US07827392B2

    公开(公告)日：2010-11-02

    申请号：US11422186

    申请日：2006-06-05

    申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Brian Michael Stempel

    发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Brian Michael Stempel

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3806 ,  G06F9/3836 ,  G06F9/3844

    摘要： A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the Branch Target Address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.

    摘要翻译： 滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签 第一个指令在块中。 这些块各自对应于从存储器获取的一组指令，例如I缓存。 在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。 滑动窗口，基于块的BTAC允许存储落在同一指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目 与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

    Virtually-tagged instruction cache with physically-tagged behavior
    69.
    发明授权
    Virtually-tagged instruction cache with physically-tagged behavior 有权
    具有物理标记行为的虚拟标记指令高速缓存

    公开(公告)号：US07802055B2

    公开(公告)日：2010-09-21

    申请号：US11468850

    申请日：2006-08-31

    申请人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

    发明人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

    IPC分类号： G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

    摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

    摘要翻译： 一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。 指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。