公开(公告)号：US07802055B2

公开(公告)日：2010-09-21

申请号：US11468850

申请日：2006-08-31

申请人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

发明人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

摘要翻译： 一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。 指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

公开(公告)号：US20070250666A1

公开(公告)日：2007-10-25

申请号：US11468850

申请日：2006-08-31

申请人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

发明人： Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Daren Eugene Streett

IPC分类号： G06F12/00

CPC分类号： G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

摘要翻译： 一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。 指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

公开(公告)号：US20140006752A1

公开(公告)日：2014-01-02

申请号：US13534649

申请日：2012-06-27

申请人： Michael William Morrow ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

发明人： Michael William Morrow ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

IPC分类号： G06F9/40

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

摘要： A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.

摘要翻译： 一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目的分支目标地址高速缓存，其中条目包括用于存储指令地址的标签字段，存储目标地址的目标字段，以及 状态字段来存储状态值。 在解码间接分支指令时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接分支指令的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目中的状态值，处理器将使用所存储的目标地址作为解码的间接分支指令的预测目标地址，或者将使用提供的软件提供的目标地址提示（如果可用）。

公开(公告)号：US08291202B2

公开(公告)日：2012-10-16

申请号：US12188626

申请日：2008-08-08

申请人： Daren Eugene Streett ,  Brian Michael Stempel

发明人： Daren Eugene Streett ,  Brian Michael Stempel

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/4812 ,  G06F12/0862

摘要： Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

摘要翻译： 描述中断处理技术。 在处理器中的指令流水线的一个或多个阶段中检测到异常情况。 响应于检测到的异常情况，并且在处理器响应于检测到的异常情况接受中断之前，检查指令高速缓存在中断处理程序的起始地址处是否存在指令。 当指令不存在于指令高速缓存中以将指令加载到指令高速缓存中时，中断向量表的起始地址处的指令从指令高速缓存上的存储器中预取，由此指令在指令高速缓存中可用 处理器响应于检测到的异常情况接受中断的时间。

公开(公告)号：US20130311760A1

公开(公告)日：2013-11-21

申请号：US13472950

申请日：2012-05-16

申请人： Kulin N. Kothari ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

发明人： Kulin N. Kothari ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3844 ,  G06F9/3848

摘要： The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

摘要翻译： 本公开涉及预测简单和多态分支指令。 本公开的实施例检测到程序指令是分支指令，确定用于分支指令的程序计数器是否存储在程序计数器滤波器中，并且如果程序计数器存储在程序计数器滤波器中，则防止程序计数器 从存储在第一级预测器中。

公开(公告)号：US09477478B2

公开(公告)日：2016-10-25

申请号：US13472950

申请日：2012-05-16

申请人： Kulin N. Kothari ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

发明人： Kulin N. Kothari ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Daren Eugene Streett

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3844 ,  G06F9/3848

摘要： The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

摘要翻译： 本公开涉及预测简单和多态分支指令。 本公开的实施例检测到程序指令是分支指令，确定用于分支指令的程序计数器是否存储在程序计数器滤波器中，并且如果程序计数器存储在程序计数器滤波器中，则防止程序计数器 从存储在第一级预测器中。

公开(公告)号：US20100036987A1

公开(公告)日：2010-02-11

申请号：US12188626

申请日：2008-08-08

申请人： Daren Eugene Streett ,  Brian Michael Stempel

发明人： Daren Eugene Streett ,  Brian Michael Stempel

IPC分类号： G06F9/30 ,  G06F13/24

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/4812 ,  G06F12/0862

摘要： Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

摘要翻译： 描述中断处理技术。 在处理器中的指令流水线的一个或多个阶段中检测到异常情况。 响应于检测到的异常情况，并且在处理器响应于检测到的异常情况接受中断之前，检查指令高速缓存在中断处理程序的起始地址处是否存在指令。 当指令不存在于指令高速缓存中以将指令加载到指令高速缓存中时，中断向量表的起始地址处的指令从指令高速缓存上的存储器中预取，由此指令在指令高速缓存中可用 处理器响应于检测到的异常情况接受中断的时间。