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公开(公告)号：US08661229B2
公开(公告)日：2014-02-25
申请号：US12434804
申请日：2009-05-04
Applicant: Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
Inventor： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
CPC classification number: G06F9/3844 , G06F9/3804
Abstract: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
Abstract translation: 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。
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公开(公告)号：US08438372B2
公开(公告)日：2013-05-07
申请号：US13212654
申请日：2011-08-18
Applicant: James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC: G06F9/30
CPC classification number: G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3863
Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
Abstract translation: 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。 当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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公开(公告)号：US20110320790A1
公开(公告)日：2011-12-29
申请号：US13212654
申请日：2011-08-18
Applicant: James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC: G06F9/38
CPC classification number: G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3863
Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
Abstract translation: 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。 当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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公开(公告)号：US20110219220A1
公开(公告)日：2011-09-08
申请号：US13108227
申请日：2011-05-16
Applicant: James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC: G06F9/38
CPC classification number: G06F9/3842 , G06F9/3806 , G06F9/3861
Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
Abstract translation: 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。 当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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5.发明授权公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
Applicant: Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
Inventor： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC: G06F12/00
CPC classification number: G06F12/126
Abstract: A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
Abstract translation: 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。
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Patent Agency Ranking
公开(公告)号：US07624254B2
公开(公告)日：2009-11-24
申请号：US11626443
申请日：2007-01-24
Applicant: Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
Inventor： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
IPC: G06F9/38
CPC classification number: G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3867
Abstract: A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
Abstract translation: 处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。
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7.发明授权公开(公告)号：US07617387B2
公开(公告)日：2009-11-10
申请号：US11535536
申请日：2006-09-27
Applicant: Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
Inventor： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
CPC classification number: G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
Abstract translation: 公开了一种在预测分支指令验证之前解决同步分支预测的方法。 该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。 该方法还包括选择一个校正状态。 如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。
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公开(公告)号：US20090210663A1
公开(公告)日：2009-08-20
申请号：US12434804
申请日：2009-05-04
Applicant: Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
Inventor： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC: G06F9/38
CPC classification number: G06F9/3844 , G06F9/3804
Abstract: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
Abstract translation: 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。
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公开(公告)号：US20090094444A1
公开(公告)日：2009-04-09
申请号：US11867727
申请日：2007-10-05
Applicant: James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC: G06F9/312
CPC classification number: G06F9/3842 , G06F9/3806 , G06F9/3861
Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
Abstract translation: 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。 当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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10.发明授权公开(公告)号：US07404042B2
公开(公告)日：2008-07-22
申请号：US11132749
申请日：2005-05-18
Applicant: Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
Inventor： Brian Michael Stempel , Jeffrey Todd Bridges , Rodney Wayne Smith , Thomas Andrew Sartorius
CPC classification number: G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
Abstract: A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
Abstract translation: 处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。 指令可能会跨越缓存行边界。 流水线处理两个地址以恢复完整的边界交叉指令。 在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。 在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。 当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。
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