Abstract:
A rake finger receiver and control method therefor, for use in a wireless spread communication system. The rake finger receiver includes a multiplexer, a searcher, a first switch fabric, a rake fingers and tracking pool, a second switch fabric, a combiner, a decoder, a channel estimator, and a rake finger controller. One searcher is used to serve multiple antennas of a base station so as to reduce the system complexity. The number of the rake fingers assigned for processing multipath components associated with a radio link is determined dynamically. Thus, the resource is utilized efficiently.
Abstract:
An orthogonal frequency-division multiplexing (OFDM) receiver that has a capability for canceling impulse interference is introduced in the present invention. The OFDM receiver includes an impulse noise remover for receiving incoming signals and canceling the impulse interference and a demodulator to demodulate the incoming signals. The impulse noise remover includes an analog-to-digital converter (ADC) that converts the incoming signals into multiple signal points, a delay line for temporarily storing the signal points, a signal processor for calculating a summation of a number of the signals points, a thresholder for checking if an input level provided by the signal processor according to the summation is greater than a predetermined threshold and a switch for replacing values of the signal points influenced by the impulse interference by zeros if the input level is greater than the predetermined threshold.
Abstract:
A data switching circuit is provided, which reduces power consumption of the source drivers when used together with a dot inversion driving method. The circuit comprises a control unit and a switching unit. Wherein, the control unit provides a switching signal. The switching unit has 2N input terminals and 2N output terminals and receives the switching signal. Assume that N is a positive integer and 1≦i≦N. When the switching signal is in a first state, the switching unit connects the (2i−1)th input terminal and the (2i−1)th output terminal, and connects the 2ith input terminal and the 2ith output terminal. When the switching signal is in a second state, the switching unit connects the 2ith input terminal and the (2i−1)th output terminal, and connects the (2i−1)th input terminal and the 2ith output terminal.
Abstract:
A serial-protocol type panel display system is suitable for use in a panel display apparatus. The panel display system includes a pixel-array display unit. Multiple divers are used to drive the pixel-array display unit to display an image. A VGA unit uses a serial protocol for encoding and exports a serial image display signal and a clock signal to the drivers. Wherein, the drivers decode the serial image display signal to obtain multiple desired displaying signals to drive the pixels of the pixel-array display unit.
Abstract:
A color management structure for a panel display is provided. It comprises: a display array unit; a plurality of gate drivers; a plurality of source drivers, the plurality of gate drivers and the plurality of source drivers driving the display array unit to display an image; and a timing sequence control unit, the timing sequence control unit outputting a plurality of signals to the plurality of gate drivers and the plurality of source drivers to drive the display array unit, the timing sequence control unit outputting a clock signal and a color management data to the plurality of source drivers.
Abstract:
A method for performing frame synchronization in a WCDMA system includes first, correlating a received signal with a plurality of predetermined correlators to obtain a plurality of frame synchronization correlation results, then, coherently combining frame synchronization correlation results with a slot synchronization phase when a test phase difference is less than a threshold phase difference, or, coherently combining frame synchronization correlation results with a linear combination of slot synchronization phases when the test phase difference is greater than or equal to the threshold phase difference. The slot synchronization phase is determined by correlating the received signal with a slot synchronization sequence. Lastly, the method determines a frame boundary of the received signal based on the coherent combination results. The method accommodates for a changing signal to noise ratio to improve frame synchronization speed and accuracy.
Abstract:
A control method for eliminating deficient display and a display device using the same and a driving circuit are provided herein. The display device includes a display panel, source driver, and a control device. The display panel includes a plurality of pixels. The source driver is used to provide a pixel voltage to the pixel. The control device determines whether to provide a first voltage to the pixels, and controls the source driver whether to provide the pixel voltage to the pixel, according to a control signal. When a system voltage of the display device is less than a predefined voltage, the control device controls the source driver to stop providing the pixel voltage to the pixel, and provides a first voltage to the pixel.
Abstract:
A soft-start high driving method and device to drive display panels are provided. The driving method includes the following steps. First, a display signal is provided for driving a display panel and displaying images. If no predetermined event happens, then, a high-driving mode is used for dynamically adjusting the driving capacity of the display signal. Finally, if a predetermined event happens, the soft-start high-driving mode is performed to dynamically adjust the driving capacity of the display signal.
Abstract:
A DVB-H receiver for performing forward error correction is disclosed. The DVB-H receiver includes: a tuner, for receiving a data stream; a base-band receiver, coupled to the tuner, for continuously extracting and transmitting data bytes of an MPE-FEC frame from the data stream; a backend system, coupled to the base-band receiver, for generating corresponding syndromes of the extracted data bytes once all data bytes of the MPE-FEC frame are received, outputting the syndromes to the base-band receiver, and forward error correcting the MPE-FEC frame according to error values corresponding to the syndromes; and a storage device, coupled to the backend system, for storing the extracted data bytes. The base-band receiver generates the error values and error locations according to the received syndromes, and then outputs the error values and error locations to the backend system.
Abstract:
A display system includes a display panel, a timing controller, a plurality of source drivers and an EDDS interface. The control signals, the clock signals and the setting signals generated by the timing controller are embedded as protocols into the data signals. The embedded signals are then transmitted from the timing controller to each source driver via a corresponding pair of differential data lines of the EDDS interface. The decoders of the source drivers can then decode the embedded signals for generating corresponding driving signals for the display panel.