公开(公告)号：US5220585A

公开(公告)日：1993-06-15

申请号：US832867

申请日：1992-02-06

申请人： Takayoshi Sasaki ,  Tsuyoshi Katayose

发明人： Takayoshi Sasaki ,  Tsuyoshi Katayose

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  H03K5/00 ,  H04L7/033

CPC分类号： H03K5/00006 ,  G06F1/08 ,  H04L7/0331

摘要： A serial clock generating circuit is configured to frequency-divide an input clock having a frequency which is a number times a serial data transfer rate, so as to generate a serial clock in phase with a received serial data. The serial clock generating circuit comprises an edge detection circuit for detecting a level change of a received serial data so as to generate a level change signal. Three registers stores different set values, and a latch latches one of the different set values. A decrementer decrements the value of the latch in response to each input clock, and a memory circuit holds an arbitrary value for defining a phase deviation discrimination area. A comparison circuit compares the value stored in the memory circuit with the value of the latch at each one input clock, and generates a coincidence signal when a coincidence is obtained. An area detection circuit discriminates a level change position on the basis of the level change signal and the coincidence signal and selects one of the registers to be set to the latch. A flipflop is coupled to the decrementer for generating a serial clock on the basis of the result of the counting of the decrementer.