公开(公告)号：US5220585A

公开(公告)日：1993-06-15

申请号：US832867

申请日：1992-02-06

申请人： Takayoshi Sasaki ,  Tsuyoshi Katayose

发明人： Takayoshi Sasaki ,  Tsuyoshi Katayose

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  H03K5/00 ,  H04L7/033

CPC分类号： H03K5/00006 ,  G06F1/08 ,  H04L7/0331

摘要： A serial clock generating circuit is configured to frequency-divide an input clock having a frequency which is a number times a serial data transfer rate, so as to generate a serial clock in phase with a received serial data. The serial clock generating circuit comprises an edge detection circuit for detecting a level change of a received serial data so as to generate a level change signal. Three registers stores different set values, and a latch latches one of the different set values. A decrementer decrements the value of the latch in response to each input clock, and a memory circuit holds an arbitrary value for defining a phase deviation discrimination area. A comparison circuit compares the value stored in the memory circuit with the value of the latch at each one input clock, and generates a coincidence signal when a coincidence is obtained. An area detection circuit discriminates a level change position on the basis of the level change signal and the coincidence signal and selects one of the registers to be set to the latch. A flipflop is coupled to the decrementer for generating a serial clock on the basis of the result of the counting of the decrementer.

公开(公告)号：US5408643A

公开(公告)日：1995-04-18

申请号：US830421

申请日：1992-02-03

申请人： Tsuyoshi Katayose

发明人： Tsuyoshi Katayose

IPC分类号： G06F9/48 ,  G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F13/26

CPC分类号： G06F11/0757 ,  G06F11/0721 ,  G06F11/0793 ,  G06F13/26 ,  Y02B60/1228

摘要： A microcomputer comprises a central processing unit, a watchdog timer generating a watchdog timer processing request when an overflow occurs in the watchdog timer, and an interrupt controller processing as a non-maskable interrupt the watchdog timer processing request generated by the watch timer. The central processing unit generates a preset signal to the watchdog timer at a beginning of execution of another interrupt processing by the central processing unit, so as to preset the watchdog timer. The interrupt controller responds to the preset signal for cancelling the watchdog timer processing request generated by the watchdog timer in a period of time of retaining the watchdog timer processing request by the interrupt controller.

摘要翻译： 微型计算机包括中央处理单元，在看门狗定时器中发生溢出时产生看门狗定时器处理请求的看门狗定时器，以及由看门狗定时器产生的看门狗定时器处理请求作为不可屏蔽中断的中断控制器。 中央处理单元在执行中央处理单元的另一中断处理开始时向看门狗定时器产生预置信号，以便预设看门狗定时器。 中断控制器响应预置信号，以在保持中断控制器的看门狗定时器处理请求的时间段内取消看门狗定时器产生的看门狗定时器处理请求。

公开(公告)号：US5497501A

公开(公告)日：1996-03-05

申请号：US147034

申请日：1993-11-01

申请人： Ichiro Kohzono ,  Tsuyoshi Katayose

发明人： Ichiro Kohzono ,  Tsuyoshi Katayose

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A data transfer controller for transferring data between a memory and a peripheral unit enhances the efficiency of the DMA transfer by performing data transfer a predetermined number of times for each transfer request from the peripheral unit. The data transfer controller comprises a first register for storing address information for accessing a source area storing data to be transferred, a second register for storing first information relative to a number of data units ready to be transferred, and a third register for storing second information relative to a number of times by which a data transfer is performed in response to each transfer request from the peripheral unit. A data transfer from the source area to a destination area is performed a number of times designated by the second information in response to each transfer request. A transfer completion signal is generated when the number of data units transferred reaches the number designated by the first information.

摘要翻译： 用于在存储器和外围单元之间传送数据的数据传输控制器通过对来自外围单元的每个传送请求执行预定次数的数据传输来提高DMA传输的效率。 数据传送控制器包括：第一寄存器，用于存储用于访问存储待传送数据的源区的地址信息;第二寄存器，用于存储相对于准备传输的数据单元的数量的第一信息;以及第三寄存器，用于存储第二信息 相对于响应于来自外围单元的每个传送请求执行数据传送的次数。 响应于每个转移请求，从源区域到目的地区域的数据传输被执行由第二信息指定的次数。 当传送的数据单元的数量达到由第一信息指定的数字时，产生传送完成信号。

公开(公告)号：US5561816A

公开(公告)日：1996-10-01

申请号：US3851

申请日：1993-01-11

申请人： Yuko Mitsuhira ,  Tsuyoshi Katayose

发明人： Yuko Mitsuhira ,  Tsuyoshi Katayose

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A data transfer controlling device of a direct memory access controller (DMAC) type includes a transfer number data storage, a transfer number updating decrementer, a data setter for setting predetermined initial data in the transfer number data storage, a terminal counter with a decrementer or an area counter with a decrementer, a memory address register, an address updating section, and a DMA execution control section. The number of times of transfer for the subsequent DMA transfer is automatically set when the number of DMA transfers to be successively executed in response to each DMA transfer request has been completed. Immediately thereafter, the DMA transfer is repeated in response to the subsequent DMA transfer request. When the DMA transfer has been completed to the final data in the DMA transfer source region of a memory, it is placed in an inhibited state. Thus, DMAC can respond to the DMA transfer request issued from a peripheral device at a high speed.

摘要翻译： 直接存储器存取控制器（DMAC）类型的数据传送控制装置包括传送号码数据存储器，传送号码更新递减器，用于设置传送号码数据存储器中的预定初始数据的数据设置器，具有减法器的终端计数器 具有减法器的区域计数器，存储器地址寄存器，地址更新部分和DMA执行控制部分。 当响应每个DMA传输请求连续执行的DMA传输次数已经完成时，自动设置随后的DMA传输的传送次数。 之后立即响应于随后的DMA传输请求重复DMA传输。 当DMA传输已完成到存储器的DMA传输源区域中的最终数据时，它被置于禁止状态。 因此，DMAC可以高速响应从外围设备发出的DMA传输请求。

公开(公告)号：US5291606A

公开(公告)日：1994-03-01

申请号：US860669

申请日：1992-03-30

申请人： Sachiko Okayama ,  Tsuyoshi Katayose

发明人： Sachiko Okayama ,  Tsuyoshi Katayose

IPC分类号： G06F9/22 ,  G06F9/48 ,  G06F13/26 ,  G06F9/46

CPC分类号： G06F13/26

摘要： In an interrupt controller, interrupt processing mode indication circuits are provided for each interrupt request circuit for storing interrupt processing mode information, and priority level indication circuits are provided for each interrupt request circuit, for storing acknowledgement order information. A search information generating circuit is provided each for generating interrupt processing mode search information and priority order search information. A search information comparison circuit detects the state of the interrupt request circuit provided for each interrupt request memory circuit, and compares the processing mode information and the acknowledgement order information with the interrupt processing mode search information and priority order search information. When the processing mode of the search information generating circuit coincides with one of the processing mode indication circuits, an internal interrupt receipt signal is generated by the search information comparison circuit in response to the interrupt request signals generated by the search information comparison circuits. When the processing mode of the search information generating circuit does not coincide with any one of the processing mode indication circuits, the processing mode search information is updated and an internal interrupt receipt signal is generated in response to the interrupt request signal generated by the search information comparison circuit when the priority order search information of the search information generating circuit perfectly coincides with the acknowledgement order information of one of the priority order indication circuits.

摘要翻译： 在中断控制器中，为每个用于存储中断处理模式信息的中断请求电路提供中断处理模式指示电路，为每个中断请求电路提供优先级指示电路，用于存储确认命令信息。 提供搜索信息生成电路，用于产生中断处理模式搜索信息和优先级顺序搜索信息。 搜索信息比较电路检测为每个中断请求存储电路提供的中断请求电路的状态，并且将处理模式信息和确认命令信息与中断处理模式搜索信息和优先级顺序搜索信息进行比较。 当搜索信息产生电路的处理模式与处理模式指示电路中的一个一致时，响应于搜索信息比较电路产生的中断请求信号，搜索信息比较电路产生内部中断接收信号。 当搜索信息产生电路的处理模式与处理模式指示电路中的任何一个不一致时，响应于由搜索信息产生的中断请求信号，更新处理模式搜索信息并产生内部中断接收信号 当搜索信息生成电路的优先顺序搜索信息与优先顺序指示电路之一的确认顺序信息完全一致时，比较电路。

公开(公告)号：US5325489A

公开(公告)日：1994-06-28

申请号：US913279

申请日：1992-07-14

申请人： Yuko Mitsuhira ,  Tsuyoshi Katayose

发明人： Yuko Mitsuhira ,  Tsuyoshi Katayose

IPC分类号： G06F13/38 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： When DMA transfer for a DMA transfer area is completed, DMA transfer for the next area may be continuously executed or stopped. In addition to this, if there is a need to urgently stop DMA transfer being executed, DMA transfer can be immediately stopped without waiting for the end of DMA transfer currently executed. For continuous DMA transfer for a plurality of DMA transfer areas, the device may be provided with an authorization bit to authorize DMA transfer operation and a next area authorization bit to authorize DMA transfer for the next area and the contents in the next area authorization bit are set to the DMA authorization bit when the terminal counter which counts the number of DMA transfer data reaches the predetermined value due to decrement. Depending on the contents in the DMA authorization bit, DMA transfer may be continued or stopped when the next DMA transfer request is generated. In addition, DMA transfer may be stopped in emergency by directly setting the applicable value at the DMA authorization bit.

摘要翻译： 当DMA传输区域的DMA传输完成时，可能会连续执行或停止下一个区域的DMA传输。 除此之外，如果需要紧急停止正在执行的DMA传输，则可以立即停止DMA传输，而无需等待当前执行的DMA传输的结束。 对于多个DMA传输区域的连续DMA传输，该设备可以被提供有授权位来授权DMA传输操作和下一区域授权位来授权下一区域的DMA传输，并且下一区域授权位中的内容是 当计数DMA传输数据的终端计数器由于递减而达到预定值时，设置为DMA授权位。 根据DMA授权位中的内容，当生成下一个DMA传输请求时，DMA传输可能会继续或停止。 此外，通过在DMA授权位上直接设置适用的值，可能会在紧急情况下停止DMA传输。

公开(公告)号：US5235682A

公开(公告)日：1993-08-10

申请号：US783756

申请日：1991-10-17

申请人： Yuko Mitsuhira ,  Tsuyoshi Katayose

发明人： Yuko Mitsuhira ,  Tsuyoshi Katayose

IPC分类号： G06F15/78 ,  H02P8/00 ,  H02P23/00 ,  H02P27/06 ,  H02P29/00

CPC分类号： H02P23/0077

摘要： A port output controller for use in a microcomputer for outputting data to a plurality of output terminals in real time, includes a latch circuit for latching data being outputted to the output terminals and a buffer register for storing data to be outputted to the output terminals next to the data being outputted to the output terminals. A timer counter counts an elapsed time after the next data has been latched in the latch circuit and causes the next data stored in the buffer register to be latched into the latch circuit when the counted elapsed time becomes a predetermined data outputting period of time. In a delayed output mode, a delay counter counts a delayed time after the next data has been latched in the latch circuit, and a delay output circuit controls the outputting of the data latched in the latch circuit to the output terminals in such a manner that if the data latched in the latch circuit is a first value, the data latched in the latch circuit is outputted to the output terminal without delay, and if the data latched in the latch circuit is a second value, the data latched in the latch circuit is outputted to the output terminal when the counted delay time has become a predetermined delay time.

公开(公告)号：US4989223A

公开(公告)日：1991-01-29

申请号：US441112

申请日：1989-11-27

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： H04L7/033

CPC分类号： H04L7/0331

摘要： A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value. A second comparison register is provided for comparing the count value of the counter with a second programmable predetermined value at each one counting operation of the counter, so as to generate a second coincidence signal when the count value of the counter is coincident with the second programmable predetermined value. A capture/comparison register operates to capture and store the count value of the counter when the level transition detection signal is generated, and also to compare the count value of the counter with the stored count value at each one counting operation of the counter, so as to generate a third coincidence signal when the count value of the counter is coincident with the stored count value. There is provided a clear circuit for generating a clear signal to the counter when either the first coincidence signal or the third coincidence signal is generated. A serial clock generator generates a serial clock signal on the basis of the second coincidence signal and the clear signal.

公开(公告)号：US5287471A

公开(公告)日：1994-02-15

申请号：US556484

申请日：1990-07-24

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed. The counter changes the contents of the third register in an opposite direction whenever memory access using the third register is performed.

摘要翻译： 一种数据传输控制器，用于控制存储区和外设之间的DMA数据传输。 数据传输控制器具有第一寄存器，其存储相对于存储器区域的预定地址的地址信息。 DMA控制单元使用第一寄存器和第二寄存器来执行存储器区域和外围单元之间的DMA数据传输。 数据传输控制器还具有用于存储用于访问DMA传输的存储区域的数据的第三寄存器。 只要存储器访问使用第三寄存器并且与存储器区域和外围单元之间的数据传输相关联的存储器访问不同，更新器被用于更新第三寄存器的内容。 最后，每当执行存储器区域和外围单元之间的数据传输时，计数器在一个方向上改变第三寄存器的内容。 当执行使用第三个寄存器的存储器访问时，计数器以相反的方向改变第三寄存器的内容。

公开(公告)号：US4930068A

公开(公告)日：1990-05-29

申请号：US118671

申请日：1987-11-09

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： A data processor comprises an interrupt processing request controller receiving processing requests from peripheral devices for generating an interrupt request. An execution unit has a first mode of executing the interrupt processing in accordance with a user's program and a second mode of executing the interrupt processing in accordance with a microprogram while maintaining an internal condition concerning execution of a program. The controller operates to selectively inhibit the execution of the interrupt processing in the first mode, but to basically allow the execution of the interrupt processing in the second mode.

摘要翻译： 数据处理器包括接收来自外围设备的处理请求以产生中断请求的中断处理请求控制器。 执行单元具有根据用户程序执行中断处理的第一模式和根据微程序执行中断处理的第二模式，同时保持关于程序执行的内部条件。 控制器操作以选择性地禁止第一模式中的中断处理的执行，而基本上允许在第二模式中执行中断处理。