公开(公告)号：US07289442B1

公开(公告)日：2007-10-30

申请号：US10613892

申请日：2003-07-02

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: H04L12/26 ,  H04L12/56 ,  G06F12/00

CPC classification number: H04L41/0896 ,  H04L47/10 ,  H04L47/125 ,  H04L47/20 ,  H04L47/215 ,  H04L47/2441 ,  H04L47/28 ,  H04L47/31 ,  H04L47/32

Abstract: A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each including a flow ID and termination bit for a corresponding packet.

Abstract translation: 配置为选择性地终止各个业务流的业务管理处理器包括：指令解码器，用于接收指定哪个业务流被删除的终止指令;以及内容可寻址存储器设备，其具有多行，每个行包括流ID和终止位， 相应的数据包。

公开(公告)号：US07283380B1

公开(公告)日：2007-10-16

申请号：US11138512

申请日：2005-05-25

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract translation: 具有选择性错误记录的内容可寻址存储器（CAM）设备。 CAM设备包括CAM阵列和错误检测电路，该电路被耦合以从CAM阵列内的所选择的存储位置接收数据值，该错误检测电路适于根据数据值是否包括错误来产生错误指示。 错误存储电路被耦合以从错误检测电路接收错误指示，并且如果错误指示指示数据值包括错误并且如果错误地址不是，则适于存储对应于所选择的存储位置的错误地址 已经存储在错误存储电路中。

公开(公告)号：US07281085B1

公开(公告)日：2007-10-09

申请号：US11047793

申请日：2005-01-31

Applicant: Ashish Garg ,  Pankaj Gupta

Inventor： Ashish Garg ,  Pankaj Gupta

IPC: G06F12/00

CPC classification number: G11C15/00 ,  H04L45/00 ,  H04L45/7453

Abstract: A system (200) can provide data aggregation with a single primary table (206) formed in a content addressable memory (CAM) section (202). Within a primary table (206) CAM entries can be part of a primary table, one or more aggregate tables, or both. In one arrangement, valid bits in each CAM entry can indicate which particular schemes a CAM entry belongs to (primary table, or any of the aggregate tables). Associated data for each table can be stored in a RAM section (204) and can be accessed according to an offset address generated according to a scheme value (i).

Abstract translation: 系统（200）可以使用形成在内容可寻址存储器（CAM）部分（202）中的单个主表（206）来提供数据聚合。 在主表（206）中，CAM条目可以是主表，一个或多个聚合表或两者的一部分。 在一种布置中，每个CAM条目中的有效位可以指示CAM条目属于哪个特定方案（主表或任何聚合表）。 每个表的关联数据可以存储在RAM部分（204）中，并且可以根据根据方案值（i）生成的偏移地址来访问。

公开(公告)号：US07237156B1

公开(公告)日：2007-06-26

申请号：US09922423

申请日：2001-08-03

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G11C29/00 ,  G11C15/00 ,  G06F12/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device having concurrent compare and error checking capability. The content addressable memory (CAM) device includes circuitry to compare a comparand with a plurality of data words stored within the CAM device in a compare operation, and circuitry to determine, concurrently with the compare operation, whether one of the data words has an error.

Abstract translation: 一种具有并发比较和错误检查功能的内容可寻址存储器（CAM）设备。 内容可寻址存储器（CAM）设备包括在比较操作中将比较与存储在CAM设备中的多个数据字进行比较的电路，以及与比较操作同时确定数据字中的一个是否具有错误的电路 。

公开(公告)号：US07237058B2

公开(公告)日：2007-06-26

申请号：US10047754

申请日：2002-01-14

Applicant: Varadarajan Srinivasan

Inventor： Varadarajan Srinivasan

IPC: G06F12/00

CPC classification number: G11C15/00 ,  H04L2012/5685

Abstract: A method and apparatus for input data selection for content addressable memory. In one embodiment, the apparatus includes an array of CAM cells, a select circuit adapted to generate a plurality of select signals each indicative of a segment of input data provided to the CAM apparatus, and switch circuitry including a plurality of programmable switch circuits each programmable to output a respective bit of the input data as a comparand bit for the array of CAM cells in response to one of the select signals.

Abstract translation: 一种用于内容可寻址存储器的输入数据选择的方法和装置。 在一个实施例中，该装置包括一个CAM单元阵列，一个选择电路，适于产生多个选择信号，每个选择信号指示提供给CAM设备的一段输入数据;开关电路包括多个可编程开关电路，每个可编程开关电路可编程 以响应于选择信号中的一个，输出用于CAM单元的阵列的比较位的输入数据的相应位。

公开(公告)号：US07230840B2

公开(公告)日：2007-06-12

申请号：US10964121

申请日：2004-10-12

Applicant: Jose P. Pereira ,  Varadarajan Srinivasan

Inventor： Jose P. Pereira ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G06F17/30982 ,  G11C15/00 ,  G11C15/04

Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.

Abstract translation: 一种具有多个CAM块和块选择电路的内容寻址存储器（CAM）装置。 每个CAM块包括一组CAM单元，用于存储具有根据配置值确定的宽度的数据字。 块选择电路包括用于接收类码的输入和用于向多个CAM块输出多个选择信号的电路。 选择信号中的每一个选择性地禁止多个CAM块中的相应一个参考比较操作，根据该类码是否与CAM块的类别分配相匹配。

公开(公告)号：US07185141B1

公开(公告)日：2007-02-27

申请号：US10271660

申请日：2002-10-16

Applicant: David V. James ,  Jagadeesan Rajamanickam

Inventor： David V. James ,  Jagadeesan Rajamanickam

IPC: G06F12/00

CPC classification number: G06F12/023 ,  G11C15/00 ,  Y02D10/13

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programmable information registers (PIRs) (104-0 and 104-1), each of which can be associated with a CAM entry set (102-0 and 102-1). PIRs (104-0 and 104-1) may be accessed in response to CAM commands. Values stores in PIRs (104-0 and 104-1) may control access to associated CAM entry sets (102-0 and 102-1) and/or be output in response to predetermined operations in an associated CAM entry set (102-0 and 102-1).

Abstract translation: 根据一个实施例，内容可寻址存储器（CAM）设备（100）可以包括多个CAM入口集合（102-0和102-1），每个CAM入口集合包括多个CAM条目。 CAM（100）还可以包括多个可编程信息寄存器（PIR）（104-0和104-1），每个可编程信息寄存器可以与CAM入口集合（102-0和102-1）相关联。 PIR（104 - 0和104 - 1）可以响应CAM命令访问。 在PIR（104-0和104-1）中存储的值可以控制对相关联的CAM条目集（102-0和102-1）的访问和/或响应于相关联的CAM条目集（102-0）中的预定操作来输出 和102-1）。

公开(公告)号：US07126834B1

公开(公告)日：2006-10-24

申请号：US10930539

申请日：2004-08-30

Applicant: Anita X. Meng ,  Eric H. Voelkel

Inventor： Anita X. Meng ,  Eric H. Voelkel

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a match condition exists when the match line (202) potential varies from the PVSS line (204) potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BB1 and/or BB2) in the sensing operation.

Abstract translation: 内容可寻址存储器（CAM）设备（200）可以在预读操作中均衡匹配线（202）和对应伪供电（PVSS）线（204）之间的电位。 在感测操作中，当匹配线（202）电位从PVSS线（204）电位变化时，感测装置（P 4）可以确定存在匹配条件。 互补的比较数据线（CD和BCD）可以在预读操作中相互均衡，而一个比较数据线（CD或BCD）可以与感测中的位线（BB 1和/或BB 2）相等 操作。

公开(公告)号：US07111123B1

公开(公告)日：2006-09-19

申请号：US10202526

申请日：2002-07-24

Applicant: Janet Zou

Inventor： Janet Zou

IPC: G06F12/02

CPC classification number: G11C15/00

Abstract: A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of the match signals. The priority encoder has a plurality of input circuits to receive the match signals from the CAM array. A priority setting circuit receives a priority transformation signal indicating a priority index for modification of the priority sequence. An encoding circuit is in communication with the plurality of input circuits and the priority setting circuit for generating the output index signal in accordance with the priority sequence. The priority encoder circuit further includes an enabling circuit for receiving an enabling signal. The enabling circuit communicates the enabling signals to the encoding circuit, such that upon deactivation of the enabling signal, the encoding circuit generates the output signal in accordance with the priority sequence with no modification by the priority setting circuit. The priority index indicates a region of the content addressable memory exempted from effective comparison. This allows the CAM array to be searched for multiple matches of the comparand. The priority index thus is an index address of the content addressable memory determined with a previous search of the content addressable memory. The priority index is provided to the priority setting circuit through a word line decoder of the array of content addressable memory cells.

Abstract translation: 内容可寻址存储器包括与内容可寻址存储器单元的阵列通信以接收匹配信号的优先编码器，以及根据匹配信号的优先顺序产生输出索引信号的匹配信号。 优先编码器具有多个输入电路，以接收来自CAM阵列的匹配信号。 优先级设置电路接收指示优先级序列的优先级索引的优先级变换信号。 编码电路与多个输入电路和优先级设定电路通信，用于根据优先顺序产生输出索引信号。 优先编码器电路还包括用于接收使能信号的使能电路。 使能电路将使能信号传送到编码电路，使得在禁用使能信号时，编码电路根据优先顺序生成输出信号，而不通过优先级设置电路进行修改。 优先级索引表示内容可寻址存储器的区域被免除有效比较。 这样可以搜索CAM阵列的比较数据的多个匹配项。 因此，优先级索引是通过先前搜索内容可寻址存储器确定的内容可寻址存储器的索引地址。 通过内容可寻址存储单元阵列的字线解码器将优先级索引提供给优先级设置电路。

公开(公告)号：US07079407B1

公开(公告)日：2006-07-18

申请号：US10273684

申请日：2002-10-18

Applicant: Dimitrios Dimitrelis

Inventor： Dimitrios Dimitrelis

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match line and adapted to differentially compare the voltage of the match line with a fixed reference voltage and, in response, generate an output signal having two or more logical states corresponding to the states of the predetermined logical relationship between the data value and the comparand data.

Abstract translation: 一种内容可寻址存储器（CAM）装置，其包括耦合到匹配线的多个CAM单元，以响应于所述CAM单元的数据值和比较数据处于预定逻辑关系而影响所述匹配线的电压，并且匹配 检测电路耦合到匹配线并且适于将匹配线的电压与固定参考电压差分比较，并且作为响应，生成具有与数据之间的预定逻辑关系的状态相对应的两个或更多个逻辑状态的输出信号 值和比较数据。