公开(公告)号：US20020035675A1

公开(公告)日：2002-03-21

申请号：US09351654

申请日：1999-07-13

Inventor： DONALD LEE FREERKSEN ,  SHELDON BERNARD LEVENSTEIN ,  GARY MICHAEL LIPPERT

IPC: G06F012/08

CPC classification number: G06F12/0831

Abstract: According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to load-load sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.

Abstract translation: 根据本发明，公开了一种用于改善对共享存储器位置的读取和写入的装置和方法。 通过给予对读取优先的写入，本发明可以减少与从共享存储器位置读取和写入的某些顺序相关联的时间。 特别地，利用本发明，将负载无效负载序列改变为负载负载序列。 此外，在使用本发明的特定情况下，共享存储器位置的争用将会减少。

公开(公告)号：US20020029321A1

公开(公告)日：2002-03-07

申请号：US09768348

申请日：2001-01-25

Inventor： Hidetaka Ebeshu ,  Hideaki Tomatsuri

IPC: G06F012/08

CPC classification number: G06F12/0882 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.

Abstract translation: 本发明是一种缓存系统，包括用于在外部存储器中存储数据的数据存储器和用于存储数据存储器中保存的数据的地址信息的标签存储器和指示由地址信息控制的数据是否有效的有效数据位; 其中，所述标签存储器中的地址信息共同地控制具有连续地址的多个数据项; 在要访问的地址对应于标签存储器中与要访问的先前地址匹配的地址信息控制的数据的情况下，禁止从标签存储器读取; 并且其中标签存储器被读取，并且在要访问的地址对应于标签存储器中与要访问的前一个地址不匹配的地址信息控制的数据的情况下执行高速缓存命中确定。

公开(公告)号：US20020026560A1

公开(公告)日：2002-02-28

申请号：US09169223

申请日：1998-10-09

Inventor： KEVIN MICHAEL JORDAN ,  KUN-LUNG WU ,  PHILIP SHI-LUNG YU

IPC: G06F012/08

CPC classification number: G06F9/505

Abstract: In a system including a collection of cooperating cache servers, such as proxy cache servers, a request can be forwarded to a cooperating cache server if the requested object cannot be found locally. An overload condition is detected if for example, due to reference skew, some objects are in high demand by all the clients and the cache servers that contain those hot objects become overloaded due to forwarded requests. In response, the load is balanced by shifting some or all of the forwarded requests from an overloaded cache server to a less loaded one. Both centralized and distributed load balancing environments are described.

Abstract translation: 在包括诸如代理缓存服务器的协作缓存服务器的集合的系统中，如果请求的对象不能在本地找到，则可以将请求转发到协作缓存服务器。 如果例如由于引用偏斜而检测到过载状况，则所有客户端都需要一些对象，并且包含这些热对象的缓存服务器由于转发请求而变得过载。 作为响应，通过将一些或全部转发的请求从重载的缓存服务器移动到较少的缓存服务器来平衡负载。 描述了集中式和分布式负载均衡环境。

公开(公告)号：US20020016886A1

公开(公告)日：2002-02-07

申请号：US09312122

申请日：1999-05-14

Inventor： J. THOMAS PAWLOWSKI ,  JOEL WATKINS

IPC: G06F012/08

CPC classification number: G06F12/0879 ,  G06F12/0855

Abstract: A memory device includes a data array, a tag array, and control logic. The data array is adapted to store a plurality of data array entries. The tag array is adapted to store a plurality of data array entries corresponding to the data array entries. The control logic adapted to access a subset of the data array entries in the data array using a burst access and to access the tag array during the burst access. A method for accessing a memory device is provided. The memory device includes a data array and a tag array. The method includes receiving a data array burst access command. The data array is accessed in response to the data array burst access command. A tag array access is received. The tag array is accessed in response to the tag array access command while the data array is being accessed.

Abstract translation: 存储器件包括数据阵列，标签阵列和控制逻辑。 数据阵列适于存储多个数据阵列条目。 标签阵列适于存储对应于数据阵列条目的多个数据阵列条目。 所述控制逻辑适于使用脉冲串访问来访问所述数据阵列中的所述数据阵列条目的子集，并且在所述突发存取期间访问所述标签阵列。 提供了一种访问存储器件的方法。 存储器件包括数据阵列和标签阵列。 该方法包括接收数据阵列突发存取命令。 响应于数据阵列突发存取命令访问数据阵列。 接收到标签数组访问。 在访问数据数组时，会对tag数组访问命令进行访问。

公开(公告)号：US20020016865A1

公开(公告)日：2002-02-07

申请号：US09828120

申请日：2001-04-09

Inventor： Hiroyuki Yanagi ,  Shinji Nakagawa ,  Motoyuki Katoh ,  Yosuke Baba

IPC: G06F009/44 ,  G06F012/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/02 ,  G06F012/04 ,  G06F012/08 ,  G06F012/10

CPC classification number: G06F9/449 ,  Y10S707/99944

Abstract: Relating to a method succeeded among a plurality of classes having a hierarchical relationship and the method overwriting the succeeded method, a method table stores therein method information including starting addresses of the storage locations of the respective methods, in which the respective method information is connected in series along the hierarchical relationship between the position classes of the respective methods. When a storage location of a message called by the message of a method call is retrieved, the retrieval of the method table is executed by the key which is the class designated by the message. Unless any designated method is retrieved by this retrieval, the key which is a super class of the designated class executes the retrieval based on the class table.

Abstract translation: 关于在具有层次关系的多个类中成功的方法和覆盖成功方法的方法，方法表存储方法信息，其中包括各方法信息所连接的各方法的存储位置的起始地址 沿着各个方法的位置类之间的层次关系。 当检索到通过方法调用的消息调用的消息的存储位置时，方法表的检索由作为消息指定的类的密钥执行。 除非通过此检索检索到任何指定的方法，否则作为指定类的超类的密钥将基于类表执行检索。

公开(公告)号：US20020002656A1

公开(公告)日：2002-01-03

申请号：US09015319

申请日：1998-01-29

Inventor： ICHIKI HONMA ,  HIROSHI KUROKAWA ,  TOSHIAKI KAWAMURA ,  EIJI NOMURA

IPC: G06F012/08

CPC classification number: G06F12/0811

Abstract: An information processing system and a multi-level hierarchical storage device for use in the information processing system having a plurality of instruction processors and a plurality of main storage devices. The multi-level hierarchical storage device includes a first-cache storage device of a write-through type provided for each instruction processor, a second-cache storage device of a write-back type provided for each main storage device, and a third-cache storage device of a write-through type provided between the first-cache storage device and the second-cache storage device.

Abstract translation: 一种在具有多个指令处理器和多个主存储装置的信息处理系统中使用的信息处理系统和多级分层存储装置。 多级分层存储装置包括为每个指令处理器提供的通过型的第一高速缓存存储装置，为每个主存储装置提供的回写类型的第二高速缓存存储装置和第三高速缓存 存储设备，其设置在第一高速缓存存储设备和第二高速缓存存储设备之间。

公开(公告)号：US20010047455A1

公开(公告)日：2001-11-29

申请号：US09837857

申请日：2001-04-17

Inventor： Dean A. Klein

IPC: G06F012/08

CPC classification number: G06F12/0811 ,  G06F12/0835 ,  G06F2212/601

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

公开(公告)号：US20010029573A1

公开(公告)日：2001-10-11

申请号：US09835215

申请日：2001-04-13

Inventor： Mark W. Johnson

IPC: G06F012/08

CPC classification number: G06F12/0864 ,  G06F12/0855 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A set-associative cache-management method combines one-cycle reads and two-cycle pipelined writes. The one-cycle reads involve accessing data from multiple sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. The two-cycle write involves finding a match in a first cycle and performing the write in the second cycle. During the write, the first stage of the write pipeline is available to begin another write operation. Also, the first-stage of the pipeline can be used to begin a two-cycle read operationnullwhich results in a power saving relative to the one-cycle read operation. Due to the pipeline, there is no time penalty involved in the two-cycle read performed after the pipelined write. Also, instead of a wait, a no-op can be executed in the first stage of the write pipeline while the second stage of the pipeline is fulfilling a write request.

Abstract translation: 集合相关缓存管理方法结合了一个周期读取和两个循环的流水线写入。 单周期读取涉及在确定标签匹配之前并行访问来自多个集合的数据。 一旦确定了标签匹配，则用于选择要与读取操作耦合到处理器的所访问的高速缓存存储单元中的一个。 双周期写入涉及在第一周期中找到匹配并在第二周期执行写入。 在写入期间，写入管道的第一阶段可用于开始另一个写入操作。 此外，流水线的第一阶段可用于开始两周期读取操作，这导致相对于单周期读取操作的省电。 由于流水线，在流水线写入之后执行的两周期读数没有时间损失。 而且，代替等待，在流水线的第二阶段满足写入请求时，可以在写入管道的第一阶段执行无操作。

公开(公告)号：US20010029572A1

公开(公告)日：2001-10-11

申请号：US09848410

申请日：2001-05-04

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Tsukasa Ooishi

IPC: G06F012/08

CPC classification number: G06F12/0804 ,  G06F12/0897 ,  Y02D10/13

Abstract: A cache DRAM includes a main memory, a main cache memory for storing data which is accessed at a high frequency out of data stored in the main memory, a main tag memory for storing an address in the main memory of the data stored in the main cache memory, a subcache memory for always receiving data withdrawn from the main cache memory for storage and supplying the stored data to the main memory when the main memory is in a ready state, and a subtag memory for storing an address in the main memory of the data stored in the subcache memory. Since the subcache memory serves as a buffer for data to be transferred from the main cache memory to the main memory, the main cache memory withdraws data to the subcache memory even if the main memory is in a busy state.

公开(公告)号：US20010008009A1

公开(公告)日：2001-07-12

申请号：US09797644

申请日：2001-03-01

Inventor： Mark W. Johnson

IPC: G06F012/08

CPC classification number: G06F12/0882 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.) However, the invention further provides for comparing the tag at the same-set location with the successor index with the tag associated with a location from which a read request was satisfied. If the next read request matches the common tag and the index of the successor location, a single-set read is also used. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial nulltag-then-datanull reads.

Abstract translation: 集相关缓存管理方法利用并行读取和单周期单集读取。 并行读取涉及在确定标签匹配之前并行访问所有高速缓存集中的数据。 一旦确定了标签匹配，则用于选择要与读取操作耦合到处理器的所访问的高速缓存存储单元中的一个。 当一个读取操作的行地址与从高速缓存满足的紧接在前的读取操作的行地址匹配时，将发生单周期单集读取。 在这种情况下，在本读取操作中仅访问满足先前读取请求的集合。 如果指示顺序读取操作，则如果所请求的地址不对应于行地址的开头，则相同集合也可以被访问以排除其他集合。 （在这种情况下，顺序读取跨越高速缓存行边界）。然而，本发明还提供了将相同位置的标签与后继索引进行比较，其中标签与满足读请求的位置相关联 。 如果下一个读取请求与公共标签和后继位置的索引相匹配，则也将使用单组读取。 单组读取相对于并行读取的保存功率，同时保持并行读取速度优于串行“标签 - 然后数据”读取的速度优势。