公开(公告)号：US20040268084A1

公开(公告)日：2004-12-30

申请号：US10611461

申请日：2003-06-30

发明人： Steve Longerbeam ,  Matthew Aaron Locke ,  Kevin Dale Morgan

IPC分类号： G06F012/08 ,  G06F012/14

CPC分类号： G06F12/145 ,  G06F16/10

摘要： Disclosed is a computing system comprising at least one random access memory (RAM) and a processor. The RAM includes a storage location containing filesystem data with associated page table entries, and each page table entry includes a read/write flag for the filesystem data. The filesystem data is initially mapped for read-only access. The processor is configured to remap the filesystem data for write access by modifying the read/write flag of the page table entries; to perform a write operation on the filesystem data in write access, and to remap the filesystem data back for read-only access by modifying the read/write flag of the page table entries. The computing system also uses filesystem that is mounted in the RAM to manage filesystem data. The filesystem protects the filesystem data from errant writes by modifying page table entries associated with the filesystem data without using a disk cache.

摘要翻译： 公开了一种包括至少一个随机存取存储器（RAM）和处理器的计算系统。 RAM包括包含具有相关页表条目的文件系统数据的存储位置，并且每个页表条目包括文件系统数据的读/写标志。 文件系统数据初始映射为只读访问。 处理器被配置为通过修改页表条目的读/写标志来重新映射用于写访问的文件系统数据; 对写入访问中的文件系统数据执行写入操作，并通过修改页表条目的读/写标志将文件系统数据重新映射回只读访问。 计算系统还使用安装在RAM中的文件系统来管理文件系统数据。 文件系统通过修改与文件系统数据相关联的页表条目而不使用磁盘缓存来保护文件系统数据免于错误的写入。

公开(公告)号：US20040268049A1

公开(公告)日：2004-12-30

申请号：US10852049

申请日：2004-05-24

发明人： Richard C. Madter

IPC分类号： G06F012/08

CPC分类号： G06F12/0888 ,  G06F12/0891 ,  G06F2212/2022

摘要： A system and method are provided for using cache memory when reading data from system memory particularly when the primary memory could include memory types other than fast read-write memory. Also, a system and method are provided for using cache memory when writing data to system memory particularly when the primary memory could include memory types other than fast read-write memory.

摘要翻译： 提供一种用于在从系统存储器读取数据时使用高速缓冲存储器的系统和方法，特别是当主存储器可以包括除快速读写存储器之外的存储器类型时。 此外，提供了一种用于在将数据写入系统存储器时使用高速缓冲存储器的系统和方法，特别是当主存储器可以包括除快速读写存储器之外的存储器类型时。

公开(公告)号：US20040268033A1

公开(公告)日：2004-12-30

申请号：US10602975

申请日：2003-06-24

申请人： Seagate Technology LLC

发明人： KokHoe Chia ,  Teck Khoon Lim ,  SanYan Liew ,  BengWee Quak

IPC分类号： G06F012/08

CPC分类号： G11B19/04 ,  G11B20/1217 ,  G11B20/1816 ,  G11B20/1883 ,  G11B20/1889 ,  G11B27/329 ,  G11B27/36 ,  G11B2005/001 ,  G11B2020/1869 ,  G11B2220/20

摘要： Data on a storage medium are refreshed by reading the data from a first location on the storage medium, storing them to a second location, and reading the data from the second location and storing them at the first location. The first and second locations are first and second physical locations and a logical address is initially associated with the first physical location. When the data are stored at the second location, the association of the logical address is changed to the second physical location. When the data are stored again at the first location, the association of the logical address is changed to the first physical address. The process is performed iteratively on the basis of successive logical block addresses. If the storing the data at the first location is interrupted, the data is re-read from the second location, and re-stored to the first location.

公开(公告)号：US20040260870A1

公开(公告)日：2004-12-23

申请号：US10463997

申请日：2003-06-17

申请人： International Business Machines Corporation

发明人： Michael E. Factor ,  Amiram Hayardeny ,  Thomas Charles Jarvis ,  Gail Andrea Spear ,  William Frank Micka ,  Sivan Tal ,  Dallt Tzafrir ,  Rivka Mayraz Matosevich ,  Sheli Rahav ,  Ifat Nuriel ,  Shachar Fienblit ,  Svetlana Shukevich

IPC分类号： G06F012/08

CPC分类号： G06F11/0727 ,  G06F11/0793 ,  G06F11/2069 ,  G06F11/2071 ,  G06F12/0866

摘要： Provided are a method, system, and program for managing a relationship between one target volume and one source volume. Information is maintained in memory on an existing relationship between at least one source volume and at least one target volume, comprising: (i) at least one element, wherein each element represents a range of sequential data units in the volume; (ii) at least one relationship entry, wherein each relationship entry represents one relationship; and (iii) at least one element pointer associating one element with one relationship entry, wherein the data units represented by the element are part of the relationship represented by the relationship entry that the pointer associates with the element. A new relationship between at least one target volume and at least one source volume is added. Further, added is a new relationship entry in the memory representing the new relationship and one new element pointer is added in the memory for each element including data units included in the new relationship to associate the element with the new relationship entry, wherein the data units represented by the element are part of the new relationship.

摘要翻译： 提供了一种用于管理一个目标卷和一个源卷之间的关系的方法，系统和程序。 信息在至少一个源卷和至少一个目标卷之间的现有关系中保存在存储器中，包括：（i）至少一个元素，其中每个元素表示该卷中的顺序数据单元的范围; （ii）至少一个关系条目，其中每个关系条目表示一个关系; 和（iii）将一个元素与一个关系条目相关联的至少一个元素指针，其中由该元素表示的数据单元是由该指针与元素相关联的关系条目表示的关系的一部分。 添加至少一个目标卷与至少一个源卷之间的新关系。 此外，添加了表示新关系的存储器中的新关系条目，并且在存储器中为包括在新关系中的数据单元的每个元素添加一个新元素指针，以将元素与新关系条目相关联，其中数据单元 由元素代表的是新关系的一部分。

公开(公告)号：US20040260869A1

公开(公告)日：2004-12-23

申请号：US10463968

申请日：2003-06-17

申请人： International Business Machines Corporation

发明人： Michael E. Factor ,  Amiram Hayardeny ,  Thomas Charles Jarvis ,  Gail Andrea Spear ,  William Frank Micka ,  Sivan Tal ,  Dalit Tzafrir ,  Rivka Mayraz Matosevich ,  Sheli Rahav ,  Ifat Nuriel ,  Shachar Fienblit ,  Svetlana Shukevich

IPC分类号： G06F012/08

CPC分类号： G06F3/065 ,  G06F3/0614 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1435 ,  Y10S707/99953 ,  Y10S707/99954

摘要： Provided are a method, system, and program for managing a relationship between one target volume and one source volume. For each of the source volume and target volume, the memory includes: (i) at least one element, wherein each element represents a range of sequential data units in the volume; (ii) at least one relationship entry, wherein each relationship entry represents one relationship; (iii) at least one element pointer associating one element with one relationship entry, wherein the data units represented by the element are part of the relationship represented by the relationship entry that the pointer associates with the element; and (iv) one relationship pointer for each relationship entry associating the relationship entry with volume metadata, wherein the volume metadata provides information on the relationship represented by the relationship entry.

摘要翻译： 提供了一种用于管理一个目标卷和一个源卷之间的关系的方法，系统和程序。 对于源卷和目标卷中的每一个，存储器包括：（i）至少一个元素，其中每个元素表示卷中的顺序数据单元的范围; （ii）至少一个关系条目，其中每个关系条目表示一个关系; （iii）将一个元素与一个关系条目相关联的至少一个元素指针，其中由该元素表示的数据单元是由指针与元素相关联的关系条目表示的关系的一部分; 以及（iv）将关系条目与卷元数据相关联的每个关系条目的一个关系指针，其中所述卷元数据提供关于由关系条目表示的关系的信息。

公开(公告)号：US20040250021A1

公开(公告)日：2004-12-09

申请号：US10882797

申请日：2004-06-30

申请人： HITACHI, LTD.

发明人： Kiyoshi Honda ,  Naoko Iwami ,  Kazuyoshi Serizawa

IPC分类号： G06F012/08

CPC分类号： G06F3/0649 ,  G06F3/0605 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0689

摘要： Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area in one of the storage devices, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.

公开(公告)号：US20040225845A1

公开(公告)日：2004-11-11

申请号：US10857819

申请日：2004-06-01

发明人： David A. Kruckemyer ,  Joseph B. Rowlands

IPC分类号： G06F012/08

CPC分类号： G06F12/0831

摘要： A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

公开(公告)号：US20040221124A1

公开(公告)日：2004-11-04

申请号：US10856081

申请日：2004-05-27

申请人： Microsoft Corporation

发明人： Richard Dennis Beckert ,  Sharon Drasnin ,  Ronald Otto Radko

IPC分类号： G06F012/08

CPC分类号： G06F11/1441 ,  G06F11/2015 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/122 ,  G06F2212/2022

摘要： Methods and systems for operating automotive computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which critical data, e.g. the object store, can be maintained in the event of a power loss. Circuitry is provided to ensure that the SRAM receives back up power from the battery at appropriate times. Software manages the SRAM and the other storage assembly components and makes use of virtual paging or virtual addressing techniques to keep track of where various pages, including object store pages, are stored in the system. The software knows where all of the object store pages are located so that in the event of a power loss, the page locations are known and hence the pages can be used when power is restored. The SRAM is advantageously used to maintain so-called nulldirty pagesnull or pages that have been written to so that these pages are not lost in the event of a power interruption. Additionally, the software can also provide an orderly means by which pages in the SRAM can be written out to flash memory thereby avoiding unnecessary flash write operations which, in turn, increases the lifetime of the flash memory.

摘要翻译： 描述了用于操作汽车计算设备的方法和系统。 在一个实施例中，少量静态RAM（SRAM）被并入到汽车计算设备中。 SRAM是电池供电的，以提供非易失性存储器空间，其中关键数据，例如， 对象存储，可以在发生电力损失的情况下维护。 提供电路以确保SRAM在适当的时间从电池接收电力。 软件管理SRAM和其他存储组件组件，并利用虚拟寻呼或虚拟寻址技术跟踪各种页面（包括对象存储页面）存储在系统中的位置。 软件知道所有对象存储页面所在的位置，以便在掉电的情况下，页面位置是已知的，因此在恢复电源时可以使用页面。 SRAM有利地用于维护已经被写入的所谓的“脏页面”或页面，使得在电源中断的情况下这些页面不会丢失。 此外，该软件还可以提供一种有序的手段，通过该方式可以将SRAM中的页面写入闪存，从而避免不必要的闪存写入操作，这又会增加闪存的使用寿命。

公开(公告)号：US20040215898A1

公开(公告)日：2004-10-28

申请号：US10425425

申请日：2003-04-28

申请人： International Business Machines Corporation

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

IPC分类号： G06F012/08

CPC分类号： G06F12/1072 ,  G06F12/1027 ,  G06F2212/682

摘要： Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a nullbarriernull class instruction.

摘要翻译： 公开了一种实现TLBI协议的对称多处理器数据处理系统（SMP），其允许来自分区内的多个处理器的多个TLBI操作同时完成。 因此，不需要全局TLB锁定，同步和TLB解锁。 当执行TLBI指令时，主机基于异步侦听另一个TLBI动态管理TLBI操作的行为。 如果需要并发TLBI管理，则主机将TLBI动态地降级为“障碍”类指令。

公开(公告)号：US20040215897A1

公开(公告)日：2004-10-28

申请号：US10425402

申请日：2003-04-28

申请人： International Business Machines Corporation

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston

IPC分类号： G06F012/08

CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

摘要： A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register includes a sequence of bits utilized to track the completion of a TLBI issued by the processor at the other processors. Each bit corresponds to a particular processor across the system and the particular processor is able to directly set the bit in the register of a master processor once the particular processor completes a TLBI operation initiated from the master processor. The master processor is able to track completion of the TLBI operation by checking the values of each bit within its TLBI register, without requiring multi-issuance of an address-only barrier operation on the system bus.

摘要翻译： 实现TLBI协议的对称多处理器数据处理系统（SMP），使多个处理器的多个TLBI操作能够完成而不会造成延迟。 每个处理器包括与TLB和TLBI逻辑相关联的TLBI寄存器。 TLBI寄存器包括用于跟踪由处理器在其他处理器发出的TLBI的完成的位的序列。 每个位对应于跨系统的特定处理器，并且特定处理器能够在特定处理器完成从主处理器发起的TLBI操作之后直接设置主处理器的寄存器中的位。 主处理器能够通过检查其TLBI寄存器中每个位的值来跟踪完成TLBI操作，而不需要在系统总线上多次发出仅地址唯一的屏蔽操作。