公开(公告)号：US12131020B2

公开(公告)日：2024-10-29

申请号：US17457615

申请日：2021-12-03

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC分类号： G06F3/06 ,  G06F11/34 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/0893

CPC分类号： G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F11/348 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

摘要： Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.

公开(公告)号：US20240248844A1

公开(公告)日：2024-07-25

申请号：US18587289

申请日：2024-02-26

申请人： Apple Inc.

发明人： Francesco Spadini ,  Gideon Levinsky ,  Mridul Agarwal

IPC分类号： G06F12/0804 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0804 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F2212/601

摘要： In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

公开(公告)号：US12039172B2

公开(公告)日：2024-07-16

申请号：US17902714

申请日：2022-09-02

申请人： Micron Technology, Inc.

发明人： Federica Cresci ,  Nicola Del Gatto ,  Emanuele Confanolieri

IPC分类号： G06F1/24 ,  G06F3/06 ,  G06F11/34 ,  G06F12/0893 ,  G06F9/4401

CPC分类号： G06F3/0613 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/349 ,  G06F12/0893 ,  G06F9/4411 ,  G06F2212/601

摘要： Provided is a system and method for storing, via a processor, in a memory of an application specific integrated circuit (ASIC), one or more threshold values responsive to at least one of physical layer and processing layer operating conditions of the ASIC. Also included is monitoring at least one of a physical layer operating condition value and a processing layer performance condition value of the ASIC, the moderating forming a monitored value, comparing the monitored value with the stored threshold values, and throttling processing layer performance of the ASIC when the monitored value exceeds at least one of the stored threshold values.

公开(公告)号：US20240020007A1

公开(公告)日：2024-01-18

申请号：US18226513

申请日：2023-07-26

申请人： Branislav Radovanovic

发明人： Branislav Radovanovic

IPC分类号： G06F3/06 ,  G06F12/0806 ,  G06F12/0804 ,  G06F12/0868

CPC分类号： G06F3/061 ,  G06F12/0806 ,  G06F3/0625 ,  G06F3/067 ,  G06F12/0804 ,  G06F12/0868 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/065 ,  G06F2212/62 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/263 ,  G06F2212/286 ,  G06F2212/502 ,  G06F2212/601

摘要： A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance. The nFE_SAN and FE_SAN controllers facilitate Converged I/O Interface by simultaneously supporting storage I/O and network traffic.

公开(公告)号：US11650919B2

公开(公告)日：2023-05-16

申请号：US17232428

申请日：2021-04-16

申请人： EMC IP Holding Company, LLC

发明人： Xiangping Chen ,  David Meiri

IPC分类号： G06F12/0804 ,  G06N20/00 ,  G06N5/04

CPC分类号： G06F12/0804 ,  G06N5/04 ,  G06N20/00 ,  G06F2212/601

摘要： A method, computer program product, and computing system for receiving, at a cache memory system, a write request for writing data to a storage system. A data reduction rate may be predicted for the write request. One or more portions of memory within the storage system may be allocated based upon, at least in part, the predicted data reduction rate for the write request. The write request may be flushed from the cache memory system to the allocated one or more portions of memory within the storage system.

公开(公告)号：US20190213178A1

公开(公告)日：2019-07-11

申请号：US16355131

申请日：2019-03-15

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： David Adamson ,  Larry Lancaster

IPC分类号： G06F16/22 ,  G06F12/08 ,  G06F12/0871 ,  G06F16/21 ,  G06F12/0873

CPC分类号： G06F16/22 ,  G06F12/08 ,  G06F12/0871 ,  G06F12/0873 ,  G06F16/217 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/601

摘要： Methods and systems for enabling sizing of storage array resources are provided. Resources of a storage array can include, for example, cache, memory, SSD cache, central processing unit (CPU), storage capacity, number of hard disk drives (HDD), etc. Generally, methods and systems are provided that enable efficient predictability of sizing needs for said storage resources using historical storage array use and configuration metadata, which is gathered over time from an install base of storage arrays. This metadata is processed to produce models that are used to predict resource sizing needs to be implemented in storage arrays with certainty that takes into account customer-to-customer needs and variability. The efficiency in which the sizing assessment is made further provides significant value because it enables streamlining and acceleration of the provisioning process for storage arrays

公开(公告)号：US20180268013A1

公开(公告)日：2018-09-20

申请号：US15462609

申请日：2017-03-17

申请人： Apple Inc.

发明人： Amir H. JADIDI ,  Rudolf PSENICNIK

IPC分类号： G06F17/30 ,  G06F12/0875 ,  G06F12/0891

CPC分类号： G06F16/2358 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0891 ,  G06F16/22 ,  G06F16/2282 ,  G06F16/2453 ,  G06F2212/465 ,  G06F2212/601

摘要： Disclosed herein are techniques for implementing a database system that provides flexible organizational aspects while retaining the ability to process and respond to database queries in an efficient manner. In particular, the techniques involve utilizing characteristics of both entity-attribute-value (EAV) database technologies and relational database technologies to provide a hybrid approach that exploits a large number of their benefits while eliminating a large number of their deficiencies. According to some embodiments, the techniques can involve implementing at least one central storage repository (configured to implement an EAV-style database), where the central storage repository provides information to at least one distributor to enable the establishment of at least one cached table (implemented in accordance with relational-style databases) within at least one cached storage device. In turn, the cached storage device can process fetch-based queries issued by client computing devices in a highly efficient manner.

公开(公告)号：US10075551B1

公开(公告)日：2018-09-11

申请号：US15174913

申请日：2016-06-06

申请人： Amazon Technologies, Inc.

发明人： Matthew Graham Baldwin ,  Ryan F. Watson

IPC分类号： G06F17/30 ,  G06F12/0811 ,  H04L29/08 ,  G06F12/0813

CPC分类号： H04L67/2842 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0897 ,  G06F2212/154 ,  G06F2212/601 ,  H04L67/327

摘要： A computer implemented cache management system and method is provided for use with a service provider configured to communicate with one or more client devices and with a content provider. The system includes a cache hierarchy comprising multiple cache levels that maintain at least some resources for the content provider, and one or more request managers for processing client requests for resources and retrieving the resources from the cache hierarchy. In response to a resource request, the request manager selects a cache level from the cache hierarchy based on a popularity associated with the requested resource, and attempts to retrieve the resource from the selected cache level while bypassing cache level(s) inferior to the selected level.

公开(公告)号：US20180173629A1

公开(公告)日：2018-06-21

申请号：US15846297

申请日：2017-12-19

申请人： EMC IP Holding Company LLC

发明人： Xinlei Xu ,  Jian Gao ,  Yousheng Liu ,  Changyu Feng ,  Geng Han

IPC分类号： G06F12/0855 ,  G06F12/0891

CPC分类号： G06F12/0855 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601

摘要： A method and system for managing a buffer device in a storage system. The method comprising determining a first priority for a first queue included in the buffer device, the first queue comprising at least one data page associated with a first storage device in the storage system; in at least one round, in response to the first priority not satisfying a first predetermined condition, updating the first priority according to a first updating rule, the first updating rule making the updated first priority much closer to the first predetermined condition than the first priority; and in response to the first priority satisfying the first predetermined condition, flushing data in a data page in the first queue to the first storage device.

公开(公告)号：US20180137042A1

公开(公告)日：2018-05-17

申请号：US15350356

申请日：2016-11-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： BRENT BEAN

IPC分类号： G06F12/02 ,  G06F12/0875 ,  G06F9/30

CPC分类号： G06F12/023 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F12/0855 ,  G06F12/0859 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0895 ,  G06F12/1054 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/452 ,  G06F2212/601 ,  G06F2212/6022 ,  G06F2212/6026

摘要： A method of retiring cache lines from a response buffer array to an icache array of a processor including providing sequential addresses to the icache array and to a response buffer array during successive clock cycles, detecting a first address hitting the response buffer array during a first clock cycle, during a second clock cycle that follows the first clock cycle, performing a first zero clock retire to write a first cache line from the response buffer array to the icache array, and during the second clock cycle, bypassing a second address which is one of the sequential addresses. The second address is bypassed given the assumption that it will likely hit the response buffer array in a subsequent cycle. If the second address missed the response buffer array, the bypassed address is replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.