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    Constant slope ramp circuits for sample-data circuits
    71.
    发明授权
    Constant slope ramp circuits for sample-data circuits 有权
    用于采样数据电路的恒定斜坡斜坡电路

    公开(公告)号：US07737732B2

    公开(公告)日：2010-06-15

    申请号：US11488550

    申请日：2006-07-18

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: H03K5/00

    CPC classification number: G11C27/024

    Abstract: A sample-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. A multiple segment ramp waveform generator is used in the sample-data analog circuits. The ramp waveform generator includes an amplifier, a variable current source, and a voltage detection circuit coupled to the current source to control the change in the amplitude of the current. The ramp generator produces constant slope within each segment regardless of the load condition. The sample-data analog circuit also utilizes variable bandwidths and thresholds.

    Abstract translation: 采样数据模拟电路包括电平交叉检测器。 电平交叉检测器控制采样开关以在电平交叉检测器感测输入信号的预定电平交叉时提供输出电压的精确采样。 在采样数据模拟电路中使用多段斜坡波形发生器。 斜坡波形发生器包括放大器，可变电流源和耦合到电流源的电压检测电路，以控制电流振幅的变化。 无论负载情况如何，斜坡发生器在每个段内产生恒定的斜率。 采样数据模拟电路还采用可变带宽和阈值。

    Reference circuits for sampled-data circuits
    74.
    发明授权
    Reference circuits for sampled-data circuits 有权

    公开(公告)号：US07616145B2

    公开(公告)日：2009-11-10

    申请号：US12178044

    申请日：2008-07-23

    Applicant: Hae Seung Lee

    Inventor： Hae Seung Lee

    IPC: H03M1/12

    CPC classification number: H03M1/1245

    Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.

    Low-voltage comparator-based switched-capacitor networks
    76.
    发明授权
    Low-voltage comparator-based switched-capacitor networks 有权
    低电压比较器开关电容网络

    公开(公告)号：US07564273B2

    公开(公告)日：2009-07-21

    申请号：US11671525

    申请日：2007-02-06

    Applicant: Matthew C. Guyton ,  Hae-Seung Lee

    Inventor： Matthew C. Guyton ,  Hae-Seung Lee

    IPC: G11C27/02

    CPC classification number: G06G7/186

    Abstract: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage. The voltage shift enables the first terminal to receive full-swing voltages when the high-limit voltage is less than twice the threshold voltage, with power supply voltages below twice the threshold voltage.

    Abstract translation: 描述了用于执行模拟电路功能的开关电容器网络和方法。 电路包括开关电容网络，比较器和电压 - 偏移网络。 开关电容器网络包括多个开关，每个开关具有相应的阈值电压并且连接到高限电压，低限电压和电接地中的一个。 与开关电容器网络通信的第一比较器输入端被配置为在第一阶段期间从其接收节点电压。 第二输入端子被配置为接收高限电压和低限电压中的一个。 电压偏移网络在第一输入端提供电压偏移，将相对于高限电压和低限电压的中间电压设置为输入参考电平。 当高电压电压低于阈值电压的两倍时，电压电压低于阈值电压的两倍，电压漂移使得第一端子能够接收全摆幅电压。

    Sampled-data circuits using zero crossing detection
    77.
    发明授权
    Sampled-data circuits using zero crossing detection 有权
    采样数据电路采用过零检测

    公开(公告)号：US07459942B2

    公开(公告)日：2008-12-02

    申请号：US11454435

    申请日：2006-06-16

    Applicant: Hae-Seung Lee

    Inventor： Hae-Seung Lee

    IPC: H03K5/22

    CPC classification number: G11C27/024 ,  H03H19/004 ,  Y10T307/74

    Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

    Abstract translation: 采样数据模拟电路包括电平交叉检测器。 电平交叉检测器控制采样开关以在电平交叉检测器感测输入信号的预定电平交叉时提供输出电压的精确采样。 电平交叉检测可以是过零检测。 可选的共模反馈电路可以保持输出共模电压基本上恒定。

    REFERENCE CIRCUITS FOR SAMPLED-DATA CIRCUITS
    78.
    发明申请
    REFERENCE CIRCUITS FOR SAMPLED-DATA CIRCUITS 有权
    采样数据电路的参考电路

    公开(公告)号：US20080278358A1

    公开(公告)日：2008-11-13

    申请号：US12178044

    申请日：2008-07-23

    Applicant: Hae Seung Lee

    Inventor： Hae Seung Lee

    IPC: H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/1245

    Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.

    Abstract translation: 开关电容器电路包括第一电平交叉检测器，用于当输入信号跨越第一预定电平时产生电平交叉检测信号。 第一波形发生器产生第一预定波形，第二波形发生器产生第二预定波形。 当所述第二预定波形第二次与电压基准电平相交时，第二电平交叉检测器产生第二电平交叉检测信号。 第二开关耦合到第二电平交叉检测器，并且第三开关耦合到第一电平交叉检测器。 当第二电平交叉检测信号第二次指示第二预定波形与电压基准电平交叉时，第二开关断开。 当第一电平交叉检测信号指示输入信号越过第一预定电平时，第三开关断开。

    CMOS active pixel with hard and soft reset
    79.
    发明授权
    CMOS active pixel with hard and soft reset 有权
    CMOS有源像素，硬复位和软复位

    公开(公告)号：US07446805B2

    公开(公告)日：2008-11-04

    申请号：US10752131

    申请日：2004-01-06

    Applicant: Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

    Inventor： Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

    IPC: H04N5/217

    CPC classification number: H04N5/3597 ,  H04N5/363 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/3745

    Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

    Abstract translation: 用于成像阵列中的像素位置的电路​​包括将入射光转换为光电流的光检测元件和可操作地连接到光检测元件的复位晶体管，以复位与光检测元件相关联的电压。 复位晶体管硬复位与光检测元件相关联的电压，并且在与光检测元件相关联的电压的硬复位产生之后，软复位与光检测元件相关联的电压。 通过将列或行线电压硬复位到第一预定电压也测量列或行线的像素电压; 将列或行线电压软复位为第一像素电压; 将列或行线电压硬复位到第二预定电压; 将列或行线电压软复位到第二像素电压; 以及确定所述第一和第二像素电压之间的差，所述差是所测量的像素电压。

    Precise CMOS imager transfer function control for expanded dynamic range imaging using variable-height multiple reset pulses
    80.
    发明授权
    Precise CMOS imager transfer function control for expanded dynamic range imaging using variable-height multiple reset pulses 有权
    精确的CMOS成像器传输功能控制，用于使用可变高度多重复位脉冲进行扩展动态范围成像

    公开(公告)号：US07417678B2

    公开(公告)日：2008-08-26

    申请号：US10751562

    申请日：2004-01-05

    Applicant: Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks

    Inventor： Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks

    IPC: H04N3/14 ,  H04N5/335 ,  H01L27/00

    CPC classification number: H04N5/35527

    Abstract: A sense node voltage relating to light intensity incident upon a light-detecting element is measured. To realize this measurement, a first integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the first integration reset pulse, an edge of the first integration reset pulse triggering a beginning of a first integration period. Thereafter, a second integration reset pulse is generated to enable a resetting of the sense node voltage to a voltage value substantially equal to a reset voltage value associated with the second integration reset pulse, an edge of the second integration reset pulse triggering a beginning of a second integration period. Subsequent to the generation of the first integration reset pulse and prior to the generation of the second integration reset pulse, a plurality of intra-period reset pulses is generated to enable resetting of the sense node voltage to a plurality of voltage values, each voltage value being substantially equal to a reset voltage value associated with the generated intra-period reset pulse. The sense node voltage generated in response to incident light intensity is measured only once during an integration period, wherein this measurement takes place subsequent to the generation of the plurality of intra-period reset pulses and prior to the generation of the second integration reset pulse.

    Abstract translation: 测量与入射到光检测元件上的光强有关的感测节点电压。 为了实现该测量，产生第一积分复位脉冲，以使感测节点电压复位为基本上等于与第一积分复位脉冲相关联的复位电压值的电压值，第一积分复位脉冲的边沿触发一个 第一个整合时期的开始。 此后，产生第二积分复位脉冲，以便将感测节点电压重置为基本上等于与第二积分复位脉冲相关联的复位电压值的电压值，第二积分复位脉冲的边沿触发一个 第二整合期。 在产生第一积分复位脉冲之后并且在产生第二积分复位脉冲之前，产生多个周期内复位脉冲，以使感测节点电压复位为多个电压值，每个电压值 基本上等于与产生的周期内复位脉冲相关联的复位电压值。 响应于入射光强度产生的感测节点电压在积分周期期间仅测量一次，其中该测量在多个周期内复位脉冲的产生之后并在第二积分复位脉冲的产生之前进行。

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